Constructive/Destructive Interference Size Padding

[mj10021]

Proposal

Problem statement

Currently, the standard library does not provide a built-in mechanism to add hardware constructive/destructive interference size padding to a struct to avoid false-sharing or promote true-sharing of instances of the same struct. These can be important tools in performance optimizations and are currently implemented independently in multiple crates.

Motivating examples or use cases

As documented in rust issue #117470, aligning a struct to the cache line size can provide significant performance benefits. Multiple crates, including mpmc::utils in rustc, crossbeam-utils, and regex implement their own version of cache padding, which would most likely be improved by std offering a built-in implementation of constructive/destructive interference size padding.

Solution sketch

A solution could look like a hard-coded value table like the implementation in crossbeam-utils, offered in rust pr #117519, although this approach is likely to be inaccurate in some cases and would require continuous updating of the values.

#[cfg_attr(
    any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "powerpc64",),
    repr(align(128))
)]
#[cfg_attr(
    any(
        target_arch = "arm",
        target_arch = "mips",
        target_arch = "mips64",
        target_arch = "riscv32",
        target_arch = "riscv64",
        target_arch = "sparc",
        target_arch = "hexagon",
    ),
    repr(align(32))
)]
#[cfg_attr(target_arch = "m68k", repr(align(16)))]
#[cfg_attr(target_arch = "s390x", repr(align(256)))]
#[cfg_attr(
    not(any(
        target_arch = "x86_64",
        target_arch = "aarch64",
        target_arch = "powerpc64",
        target_arch = "arm",
        target_arch = "mips",
        target_arch = "mips64",
        target_arch = "riscv32",
        target_arch = "riscv64",
        target_arch = "sparc",
        target_arch = "hexagon",
        target_arch = "m68k",
        target_arch = "s390x",
    )),
    repr(align(64))
)]

Other approaches are offered by the C++ implementation, linked below. Additionally, LLVM offers built-in methods for getting target arch cache line sizes.

Alternatives

Links and related work

Zulip discussion: https://rust-lang.zulipchat.com/#narrow/stream/327149-t-libs-api.2Fapi-changes/topic/adding.20CachePadded.20to.20std

Existing implementations: crossbeam-utils: https://docs.rs/crossbeam/latest/crossbeam/utils/struct.CachePadded.html mpmc-utils: https://doc.rust-lang.org/beta/src/std/sync/mpmc/utils.rs.html

This feature exists in C++ as std::hardware_destructive_interference_size and std::hardware_constructive_interference_size, https://en.cppreference.com/w/cpp/thread/hardware_destructive_interference_size . The original paper describing the feature offers a few possible implementations: https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0154r1.html .

LLVM GetCacheLineSize: https://llvm.org/doxygen/classllvm_1_1MCSubtargetInfo.html#ac4be4ef1a969f0da1aa2da9aa5ccfe45

What happens now?

This issue contains an API change proposal (or ACP) and is part of the libs-api team feature lifecycle. Once this issue is filed, the libs-api team will review open proposals as capability becomes available. Current response times do not have a clear estimate, but may be up to several months.

Possible responses

The libs team may respond in various different ways. First, the team will consider the problem (this doesn't require any concrete solution or alternatives to have been proposed):

• We think this problem seems worth solving, and the standard library might be the right place to solve it.
• We think that this probably doesn't belong in the standard library.

Second, if there's a concrete solution:

• We think this specific solution looks roughly right, approved, you or someone else should implement this. (Further review will still happen on the subsequent implementation PR.)
• We're not sure this is the right solution, and the alternatives or other materials don't give us enough information to be sure about that. Here are some questions we have that aren't answered, or rough ideas about alternatives we'd want to see discussed.