Open rminnich opened 4 years ago
Already reported to upstream crate: https://github.com/rust-lang/compiler-builtins/issues/322
here is the "fix" for oreboot
`+.globl atomic_store_16 +atomic_store_16:
i.e. fake up no op atomic load and store for 16 bits, b/c the architecture does not support them.
You're asking the architecture to do something it can't do ... :-p
sorry about the format, that's what github claims is a code copy/paste? ` +.globl atomic_store_16 +atomic_store_16:
Copying comment from https://github.com/oreboot/oreboot/issues/183#issuecomment-552965077 CC @lenary IIRC In the GCC world this symbol is provided by libatomic rather than libgcc directly. In the LLVM world, compiler-rt provides the symbol. Rust should either use a RISC-V compiler-rt or if using libgcc it should link libatomic as well.
Yeah. This issue comes up every so often, especially more recently.
The RISC-V "A" extension only introduces instructions for 32- and 64-bit atomic operations. If you need up-to-32-bit atomic operations (ie, 8-bit or 16-bit atomic operations), then you have to link with -latomic
if using gcc's compiler builtins (because libgcc and libatomic are separate libraries).
LLVM's compiler-rt is a slightly different, and contains both the compiler builtins and the atomic libcalls in the same library, so this issue should arise less once LLVM can switch to compiler-rt for RISC-V. That could happen soon given https://reviews.llvm.org/D68393 has landed.
I was fixed in compiler-builtins crate via https://github.com/rust-lang/compiler-builtins/pull/324. Can you make xargo pull newer version? Otherwise it may require updating this dependency in Rust repo.
@rminnich @lenary is this issue now fixed?
We have been building github.com/oreboot/oreboot with rust since last spring. Within the last month, we've hit the problem seen in https://dev.azure.com/azure0427/Oreboot%20Pipeline/_build/results?buildId=338, as well as https://github.com/oreboot/oreboot/issues/183
atomic_store_16 is undefined, as is atomic_load_16.
oreboot has been working on riscv hardware (riscv64, sifive hifive board) for several months, so we're not quite sure where to start. I've been looking around for similar problems but nothing quite fits.
Thanks.