Closed sayantn closed 4 weeks ago
That does seem like an oversight, feel free to send a PR to fix it! Also, could you check if any similar mistakes have been made for other intrinsics?
I could not find any more such oversights. I will send a PR.
There is also issues in x86 feature detection in Alderlake. Some Alderlake CPUs do have the "AVX512" instructions VAES, VPCLMULQDQ and GFNI, even though they do not have any other AVX512 instructions.
rustc --print cfg --target-cpu=native
does print that these instructions are supported, but is_x86_feature_detected
returns false for these features. Using these instructions return the correct result too (no SIGILL).
That can be fixed in the feature-detection logic for AVX512 in crates/std_detect/src/detect/os/x86.rs.
According to [Intel Intrinsics Guide] (https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html) the
_mm256_cvtsd_f64
intrinsic should be enabled with AVX, but the rust function hastarget_feature
AVX2. This makes it unable to inline with AVX only, but AVX cpus do have thevmovsd
instruction