sethp
commented
1 year ago I love this analysis: great work, and an excellent writeup! Do we know for sure the polarity of Half matches the clock? I think we do, now that we're resetting the GAL, right?
a delay signal between 11ns and 25ns (exclusive)
Huh, when you put it that way, it almost feels like we want a double-speed clock to AND or NAND with here; we could get that if we had an edge-triggered clock coupled to the SPI clock, right? An edge detector is just ANDing a NOT'd signal with itself to produce a brief pulse, could we use that to double-clock a flip-flop somewhere? There's also this article, that I haven't gone through yet, but sure seems relevant (especially the part about abusing 7400 chips): https://dqydj.com/how-to-double-clock-frequency-using-only-digital-logic/
So we seem to have a range of timing requirements and it'd be great to have a way to characterize the whole system in terms of the timing requirements while being able to vary the number of NOT gates we use in a given signal path as well as what delay in the NOT gates.
One potentially goofy idea I had this morning was to hook up a potentiometer along the VCC path to an inverter chip: at least for the 74HC04s I have, they seem to get a lot slower at lower supply voltages. In my head, we'd use the pot to vary between ~5 or 6ns of delay per gate up to ~25ns or so so we could get a tactile sense of how wide our timing windows actually are.
It'd be a little tricky to set up, I think, since the effective resistance of the chip (V=IR with 2µA max current at 6V suggests ~3MΩ impedance) is pretty massive relative to the potentiometers I've got on hand (ideally we'd have a pot that goes from ~0Ω to 3/6MΩ, but the beefiest one I can find right now on my desk is a mere 10kΩ). We could cobble together something similar from a chain of resistors, but I really like the idea of feeling out the boundaries with a knob; maybe we drop a ~5kΩ resistor in parallel with the inverter?
In designing the PCB for the esp32c3 dev board and SPI pixel byte output I've started to consider the issue of the
w̅write signal which will take the output byte every other SPI cycle from the SIPO and write it into the FIFO ram.Then when the inverted pixel clock is low we read the FIFO (called
r̅), and the byte is subsequently saved in a register when the invertedr̅goes low. Here we are using the NOT gate delay to ensure we have proper setup time from the read byte from the FIFO.In the above diagram I have one NOT gate from the
Halfsignal of the SIPO into thew̅. But alternatively we could have 3 NOT gates to increase a delay, or we could source signal from~Halffrom the SIPO and use an even number of NOT gates: 2 or 4.The FIFO has timing requirements:
w̅signal must go low for 15 ns (which is no problem for us)Of note is the
~Halfsignal from the SIPO is delayed fromHalfby about 2 ns.So it seems our timing window is guaranteed if we introduce a delay signal (in the proper "polarization" so to speak (where our
w̅signal is rising during the valid data time)) between 11ns and 25ns (exclusive) fromHalf, or 9ns and 23ns from~Half.We can use an odd number of NOT gates from
Half, and an even number of NOT gates from~Half.Some other factors we need to think about though is that the Pixel Clk is also being inverted and that should probably happen as fast as possible, and we invert it again to save the data into the output register, which should be not quite as fast as possible. So we seem to have a range of timing requirements and it'd be great to have a way to characterize the whole system in terms of the timing requirements while being able to vary the number of NOT gates we use in a given signal path as well as what delay in the NOT gates.
So maybe 3 equations and 2 unknowns? Mostly just curious what your thoughts might be and if maybe you have a different way of looking at all this.