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ryotaroAAA / pynes

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CPU cycle の計算が nestest と合わない問題 #1

Open ryotaroAAA opened 3 years ago

ryotaroAAA commented 3 years ago 
[sample] 
4756 E3A9 STA   ABS_X   0633 A:44 X:00 Y:66 P:67 SP:00FB PPU:121 157 CYC:13806
4757 E3AC LDA   ABS     0633 A:44 X:00 Y:66 P:67 SP:00FB PPU:121 169 CYC:13810
[correct] 
4756 E3A9 STA           0000 A:44 X:00 Y:66 P:67 SP:00FB PPU:121 157 CYC:13806
4757 E3AC LDA           0000 A:44 X:00 Y:66 P:67 SP:00FB PPU:121 172 CYC:13811

例えば STA ABS_X。X:00 なのでページクロス発生しないはず。4クロックのハズが5...？

http://pgate1.at-ninja.jp/NES_on_FPGA/nes_cpu.htm

Absolute,X STA $4400,X $9D 3 4 +1

https://wiki.nesdev.com/w/index.php?title=CPU_addressing_modes

a,x | Absolute indexed | val = PEEK(arg + X) | 4+

  • +means add a cycle for write instructions or for page wrapping on read instructions, called the "oops" cycle below.
  • To calculate a,x or a,y addressing in an instruction other than sta, stx, or sty, it uses the 8-bit ALU to first calculate the low byte while it fetches the high byte.
  • If there's a carry out, it goes "oops", applies the carry using the ALU, and repeats the read at the correct address.
  • Store instructions always have this "oops" cycle: the CPU first reads from the partially added address and then writes to the correct address.
  • The same thing happens on (d),y indirect addressing.
ryotaroAAA commented 3 years ago

クロックは真面目に合わせなくても良い説もあるので気楽に