Open Fish-Git opened 4 years ago
s390guy
commented
4 years ago Thank you. First contribution from someone else!
The POPCNT change will require a different (probably new) instruction format. Formats are a bit more complex.
Again, thanks. Will let you know when the SATK is updated.
Fish-Git
commented
4 years ago Something else I was unable to do was define the extended mnemonics for the BIC (Branch Indirect on Condition) instruction.
The normal non-extended-mnemonic assembler format is:
BIC M1,D2(X2,B2)The extended-mnemonic assembler format is:
BIxx D2(X2,B2)where BIxx is one of:
BIZ/BIE B'1000' (zero/equal)
BIM/BIL B'0100' (minus/low)
BIP/BIH B'0010' (plus/high)
BIO B'0001' (overflow/ones)
BINZ/BINE B'0111' (not zero/not equal)
BINM/BINL B'1011' (not minus/not low)
BINP/BINH B'1101' (not plus/not high)
BINO B'1110' (not overflow/not ones)
BI B'1111' (unconditional)I looked at how you were already doing it in your formats.msl file, but it appears you are simply defining the mask field as an extended opcode field instead, BUT...
The BIC instruction, already being an extended opcode instruction, already has an extended opcode field defined for byte 5 of the instruction, so I'm confused as to how to define them.
Hopefully you can figure that out for us too. :)
Thanks!
Fish-Git
commented
4 years ago FYI: Extended mnemonics also exist for the "Select" (SELR, SELGR) and "Select High" (SELFHR) instructions as well:
(https://www.ibm.com/support/pages/high-level-assembler-support-ibm-z15-instructions-apar-ph00902)
SELR:
selrE B'1000' selrL B'0100' selrH B'0010' selrNE B'0111' selrNL B'1011' selrNH B'1101' selrZ B'1000' selrM B'0100' selrP B'0010' selrO B'0001' selrNZ B'0111' selrNM B'1011' selrNP B'1101' selrNO B'1110'
SELGR:
selgrE selgrL selgrH selgrNE selgrNL selgrNH selgrZ selgrM selgrP selgrO selgrNZ selgrNM selgrNP selgrNO
SELFHR:
selfhrE selfhrL selfhrH selfhrNE selfhrNL selfhrNH selfhrZ selfhrM selfhrP selfhrO selfhrNZ selfhrNM selfhrNP selfhrNO
s390guy
commented
4 years ago Again new formats will be required in the MSL file for these extended mnemonics. Not a problem. And, thanks for the research on this information. I certainly would not have found the link to the z15 instructions. As soon as I can get to it, I will.
s390guy
commented
4 years ago On Fri, 2020-10-02 at 11:53 -0700, Fish-Git wrote:
The following patch adds most () of the support needed for the Miscellaneous-Instruction-Extensions Facility 2 and 3 instructions: From: "'Fish' (David B. Trout)" fish@infidels.orgDate: Fri, 02 Oct 2020 11:31:13 -0800Subject: [PATCH] Miscellaneous-Instruction- Extensions Facility 2 and 3 () The only thing it doesn't fix is the change to the POPCNT instruction introduced with Miscellaneous-Instruction-Extensions Facility 3: the instruction format changed from RRE to RRF-a instead. Previously, the RRE format POPCNT instruction only supported two operands: R1,R2. With the introduction of the Miscellaneous-Instruction-Extensions Facility 3 however, it's now an RRF-a format instruction supporting an optional M3 operand: R1,R2[,M3]. I couldn't quite figure out how to do that, so I leave that last little bit to you. :) Just trying to help!
Something you and the other interested parties should know about ASMA: Steve Orso ran into a similar problem with some of the FP instructions he was working with. At the time he was the only active user. The easiest way at the time to handle the issue was to make all operands optional. So by just defining POPCNT with three operands in the MSL file will achieve the desired result. When coding the optional operand, just leave it off and it will default to zero. (In fact that is true for any operand. An instruction with no operands results in an instruction with the opcode and everything else being set to zero.) I did a quick look and do not think this is documented in the manual. Probably should be. The last time this came up, Steve did not want to change this behavior. So, I figure some ASMA based tests are dependent upon the behavior so here we are. Harold Grovesteen
Fish-Git
commented
3 years ago @s390guy
The easiest way at the time to handle the issue was to make all operands optional. So by just defining POPCNT with three operands in the MSL file will achieve the desired result.
So how the heck do I do that?! :(
s390guy
commented
3 years ago OK. To be clearer. In the MSL file, POPCNT is defined as if all three operands are required. The MSL file knows nothing about what is coded in the actual assembler statement. You would then simply code the POPCNT instruction in your statement leaving out whichever operands that are optional. You could leave all of them out if you choose. For omitted operands, ASMA uses a binary value of zeros for each bit used by the operand.
The MSL file is a resource used to build the instruction as coded by the source statement. When an operand is coded, the MSL file informs ASMA as to how to place that piece of information into the machine instruction. If the user coded assembler statement omits an operand by leaving it off or simply coding a comma for the next operand, the MSL file is not referenced and the initialized value for the instruction (binary zeros for all bits other than the opcode) do not get replaced.
Operands required or optional are unknown to the MSL file. All operands are defined in the format and it is only used when the source operand is present.
This means no error messages for omitted operands, although if you code the wrong things, a value might not fit.
Usually the assembler statement is coded by a user the way they would with any other assembler and nobody really notices this feature (it is working as designed, just perhaps a bit differently than a user might expect). Admittedly, this feature is a quick and dirty response to needing optional operands. Originally, all operands were required.
Fish-Git
commented
3 years ago THANK YOU, Harold. I get it now. My mistake was in believing the MSL files each played a larger role than what they actually in fact do. I saw your comments in the MSL files saying certain operands were required, and couldn't figure out how to make the changes necessary to make an operand optional. Based on your explanation however, I now see that was a wild goose chase. A red herring. It is the ASMA component that is responsible for determining which operands are required and which are optional, where, from you just told me, ALL operands for ANY/ALL instructions are technically optional as far as ASMA is concerned! I was not aware of that fact and certainly did not expect such behavior! (which is quite different from the way other assemblers behave of course)
Something else that added to my confusion was that when I tried coding my POPCNT statement with the new Miscellaneous-Instruction-Extensions Facility 3 optional 3rd operand, ASMA was throwing an error (which I probably didn't look closely enough at). It was only when I noticed it was defined in your MSL files as an RRE format instruction instead of as an RRFC (RRF-c) format instruction that the mental connection was finally made. Once I changed it to RRFC format, then it compiled perfectly, both with or without the optional 3rd operand.
All is well now. :)
Attached is my patch to add the missing Miscellaneous-Instruction-Extensions Facility 3 instructions, which I noticed you haven't added yet for some reason. You added the new Miscellaneous-Instruction-Extensions Facility 2 instructions, but not the Miscellaneous-Instruction-Extensions Facility 3 instructions yet for some reason.
Anyway, here's my patch:
(inlined):
From: "User Name" <user@example.com>
Date: Sat, 23 Jan 2021 11:35:59 -0800
Subject: [PATCH] Short description
Details of change, perhaps spanning...
...multiple...
...lines.
diff -r -a -x .git -x 'msvc.AMD64.*' -x 'msvc.dllmod.*' -x 'msvc.debug.*' -x '*.suo' -x '*.ncb' -x '*.user' -x '*.htm' -x WORK -x DICTS -x FILES -x 'allTests.*' -x '*.rej' -x '*.orig' -x AutoBuildCount.h -x '*.cmp*' -x '*.comp*' -Nu b/all-insn.msl a/all-insn.msl
--- b/all-insn.msl 2021-01-22 14:05:56.306823800 -0800
+++ a/all-insn.msl 2021-01-23 11:06:48.407079000 -0800
@@ -244,6 +244,7 @@
features s390x-insert-ref-bits-multiple # September, 2017
features s390x-msa-8 # September, 2017
features s390x-misc-inst-ext-2 # September, 2017
+ features s390x-misc-inst-ext-3 # September, 2019
features s390x-test-ext-intrp # September, 2017
features s390x-vector-enh-fac-1 # September, 2017
features s390x-vector-packed-1 # September, 2017
@@ -1878,6 +1879,27 @@
iset s390x-misc-inst-ext-2
mnemonics AGH BIC MG MGRK MGH MSC MSRKC MSGC MSGRKC SGH
+# MISCELANEOUS-INSTUCTIONS-EXTENSION FACILITY 3
+inst NCRK B9F5 RRFA1 # AND WITH COMPLEMENT (32)
+inst NCGRK B9E5 RRFA1 # AND WITH COMPLEMENT (64)
+inst MVCRL E50A SSE2 # MOVE RIGHT TO LEFT
+inst NNRK B974 RRFA1 # NAND (32)
+inst NNGRK B964 RRFA1 # NAND (64)
+inst NORK B976 RRFA1 # NOR (32)
+inst NOGRK B966 RRFA1 # NOR (64)
+inst NXRK B977 RRFA1 # NOT EXCLUSIVE OR (32)
+inst NXGRK B967 RRFA1 # NOT EXCLUSIVE OR (64)
+inst OCRK B975 RRFA1 # OR WITH COMPLEMENT (32)
+inst OCGRK B965 RRFA1 # OR WITH COMPLEMENT (64)
+inst SELR B9F0 RRFA2 # SELECT (32)
+inst SELGR B9E3 RRFA2 # SELECT (64)
+inst SELFHR B9C0 RRFA2 # SELECT HIGH (32)
+
+# See IBM z/Architecture Principles of Operation, SA22-7832-12, September, 2019
+# MI3 instructions
+iset s390x-misc-inst-ext-3
+ mnemonics NCRK NCGRK MVCRL NNRK NNGRK NORK NOGRK NXRK NXGRK OCRK OCGRK SELR SELGR SELFHR
+
# MOVE-WITH-OPTIONAL-SPECIFICATIONS FACILITY (February, 2008)
inst MVCOS C80 SSF2 # MOVE WITH OPTIONAL SPECIFICATIONS
@@ -1908,10 +1930,13 @@
# POPULATION COUNT FACILITY (August, 2010)
-inst POPCNT B9E1 RRE # POPULATION COUNT
+# MISCELANEOUS-INSTUCTIONS-EXTENSION FACILITY 3 (September, 2019)
+inst POPCNT B9E1 RRFC # POPULATION COUNT
# See IBM z/Architecture Principles of Operation, SA22-7832-08, August, 2010
# PK instruction
+# See IBM z/Architecture Principles of Operation, SA22-7832-12, September, 2019
+# MI3 instructions
iset s390x-pop-count
mnemonics POPCNT
diff -r -a -x .git -x 'msvc.AMD64.*' -x 'msvc.dllmod.*' -x 'msvc.debug.*' -x '*.suo' -x '*.ncb' -x '*.user' -x '*.htm' -x WORK -x DICTS -x FILES -x 'allTests.*' -x '*.rej' -x '*.orig' -x AutoBuildCount.h -x '*.cmp*' -x '*.comp*' -Nu b/formats.msl a/formats.msl
--- b/formats.msl 2021-01-22 14:05:56.322423800 -0800
+++ a/formats.msl 2021-01-23 11:12:24.969614100 -0800
@@ -614,8 +614,8 @@
# | OP | XOP | M3 |0000 | R1 | R2 |
# +-----+-----+-----+-----+-----+-----+-----+-----+
#
-# RRFC: MNEMONIC R1,R2,M3
-# Note: M3 is not optional
+# RRFC: MNEMONIC R1,R2[,M3]
+# Note: M3 is SOMETIMES optional
#
format RRFC
length 4
diff -r -a -x .git -x 'msvc.AMD64.*' -x 'msvc.dllmod.*' -x 'msvc.debug.*' -x '*.suo' -x '*.ncb' -x '*.user' -x '*.htm' -x WORK -x DICTS -x FILES -x 'allTests.*' -x '*.rej' -x '*.orig' -x AutoBuildCount.h -x '*.cmp*' -x '*.comp*' -Nu b/s390x-insn.msl a/s390x-insn.msl
--- b/s390x-insn.msl 2021-01-22 14:05:56.322423800 -0800
+++ a/s390x-insn.msl 2021-01-23 11:07:56.457209000 -0800
@@ -104,6 +104,7 @@
features s390x-insert-ref-bits-multiple # September, 2017
features s390x-msa-8 # September, 2017
features s390x-misc-inst-ext-2 # September, 2017
+ features s390x-misc-inst-ext-3 # September, 2019
features s390x-test-ext-intrp # September, 2017
features s390x-vector-enh-fac-1 # September, 2017
features s390x-vector-packed-1 # September, 2017
@@ -1704,6 +1705,27 @@
iset s390x-misc-inst-ext-2
mnemonics AGH BIC MG MGRK MGH MSC MSRKC MSGC MSGRKC SGH
+# MISCELANEOUS-INSTUCTIONS-EXTENSION FACILITY 3
+inst NCRK B9F5 RRFA1 # AND WITH COMPLEMENT (32)
+inst NCGRK B9E5 RRFA1 # AND WITH COMPLEMENT (64)
+inst MVCRL E50A SSE2 # MOVE RIGHT TO LEFT
+inst NNRK B974 RRFA1 # NAND (32)
+inst NNGRK B964 RRFA1 # NAND (64)
+inst NORK B976 RRFA1 # NOR (32)
+inst NOGRK B966 RRFA1 # NOR (64)
+inst NXRK B977 RRFA1 # NOT EXCLUSIVE OR (32)
+inst NXGRK B967 RRFA1 # NOT EXCLUSIVE OR (64)
+inst OCRK B975 RRFA1 # OR WITH COMPLEMENT (32)
+inst OCGRK B965 RRFA1 # OR WITH COMPLEMENT (64)
+inst SELR B9F0 RRFA2 # SELECT (32)
+inst SELGR B9E3 RRFA2 # SELECT (64)
+inst SELFHR B9C0 RRFA2 # SELECT HIGH (32)
+
+# See IBM z/Architecture Principles of Operation, SA22-7832-12, September, 2019
+# MI3 instructions
+iset s390x-misc-inst-ext-3
+ mnemonics NCRK NCGRK MVCRL NNRK NNGRK NORK NOGRK NXRK NXGRK OCRK OCGRK SELR SELGR SELFHR
+
# MOVE-WITH-OPTIONAL-SPECIFICATIONS FACILITY (February, 2008)
inst MVCOS C80 SSF2 # MOVE WITH OPTIONAL SPECIFICATIONS
@@ -1734,10 +1756,13 @@
# POPULATION COUNT FACILITY (August, 2010)
-inst POPCNT B9E1 RRE # POPULATION COUNT
+# MISCELANEOUS-INSTUCTIONS-EXTENSION FACILITY 3 (September, 2019)
+inst POPCNT B9E1 RRFC # POPULATION COUNT
# See IBM z/Architecture Principles of Operation, SA22-7832-08, August, 2010
# PK instruction
+# See IBM z/Architecture Principles of Operation, SA22-7832-12, September, 2019
+# MI3 instructions
iset s390x-pop-count
mnemonics POPCNT
Thanks again for such a GREAT product! SATK/ASMA rocks! :-D
Fish-Git
commented
3 years ago Attached is my patch to add the missing Miscellaneous-Instruction-Extensions Facility 3 instructions ...
Which ALSO fixes the POPCNT instruction as well, to account for its new optional 3rd operand introduced with Miscellaneous-Instruction-Extensions Facility 3.
Be well. Stay safe.
s390guy
commented
3 years ago POPCNT, SSKE have been modified for s390x, 24, 31, 64 assembler targets now using the RRFC MSL instruction format. Missing IVSK has been added for the s370 target. Later targets included IVSK. Miscellaneous-Instruction-Extensions Facility 3 has been added to s370, 24, 31, and 64 assembler targets.
These changes were contributed by Fish (David B. Trout) as per the above patch.
s390guy
commented
3 years ago This issue is being kept open because it touches upon extended mnemonics not yet supported by ASMA. More recent extended mnemonics go beyond the present ability of ASMA which is limited to setting the values in conditional masks that reside in the second byte of instructions. The Machine Specification Language (MSL) must be enhanced to support such mnemonics and then the extended mnemonics must be added to the assembler.
The base instructions are supported. So, as a work around until the enhancements are made, a simple local macro will allow use of extended mnemonics within any source code making use of the base instruction.
Fish-Git
commented
3 years ago POPCNT, SSKE have been modified for s390x, 24, 31, 64 assembler targets now using the RRFC MSL instruction format. Missing IVSK has been added for the s370 target. Later targets included IVSK. Miscellaneous-Instruction-Extensions Facility 3 has been added to s370, 24, 31, and 64 assembler targets.
Thank you! Much appreciated!
More recent extended mnemonics go beyond the present ability of ASMA ... The Machine Specification Language (MSL) must be enhanced to support such mnemonics and then the extended mnemonics must be added to the assembler.
Hmmm... Okay. I wasn't aware of that.
The base instructions are supported. So, as a work around until the enhancements are made, a simple local macro will allow use of extended mnemonics within any source code making use of the base instruction.
Understood and accepted. Will do. As I explained in my private email to you, most of the new extended mnemonics I don't need right away (i.e. there's no real rush/urgency to get any of them implemented), so your proposed interim workaround is completely acceptable and just fine.
Good luck with your MSL redesign! Take your time and do a good job. I'm sure I speak for everyone in my saying that we all very much appreciate your having created SATK/ASMA in the first place. It is a very valuable (nay, indispensible!) tool not only for Hercules developers but also to the Hercules community at large. Thank you, Harold!
s390guy
commented
2 years ago ASMA is current with the latest PoO -13 manual in its support of machine instructions.
Extended mnemonics are being implemented. Extended mnemonics for Miscellaneous-Instructions-Extensions Facility 2 and 3 are yet to be implemented. Facility 2 was made available with the -11 version of the PoO. Facility 3 with the -12 version.
As of writing this comment, extended mnemonic work for general instructions (Chapter 7 of PoO) is ongoing for the -08 version. So, -11 and -12 general instruction extended mnemonics are still planned for implementation. The key item is there is now a plan that is being worked to get the missing extended mnemonics implemented.
The following patch adds most *`()`** of the support needed for the Miscellaneous-Instruction-Extensions Facility 2 and 3 instructions:
*`()`** The only thing it doesn't fix is the change to the
POPCNTinstruction introduced with Miscellaneous-Instruction-Extensions Facility 3: the instruction format changed fromRREtoRRF-cinstead.Previously, the RRE format
POPCNTinstruction only supported two operands: R1,R2.With the introduction of the Miscellaneous-Instruction-Extensions Facility 3 however, it's now an RRF-c format instruction supporting an optional M3 operand: R1,R2[,M3].
I couldn't quite figure out how to do that, so I leave that last little bit to you.
:)Just trying to help!
Here's the patch as a downloadable text file:
FYI: you might need to run it through d2u (dos2unix) to fix the line endings first before attempting to apply it.