Recorder in timing core

[vijay4454]

I am trying to understand the difference between timing core and simple core model. I see that the timing core model has the "recorder", presumably to record events. I am not quite sure what that means. What is the use case of the timing core over the simple core, given that my objective is to have a 1 IPC simulation where the memory instructions go through the cache hierarchy and hence take more than 1 cycle on cache misses. Both types of cores seem to satisfy my objective.

[gaomy3832]

Only the cores with event recorders can be used with weave model structures (TimingCache, DetailedMemory, DDRMemory, etc.). The recorder stores the events that are created in bound phase and are needed to simulate in weave phase.

So, if you don't have weave model structures in your system, they are the same. But if you have, then SimpleCore doesn't work.

[vijay4454]

Thanks a lot! That was useful to know.

[vijay4454]

I have a follow up question here. I have read the ZSim ISCA paper and more-or-less understand the bound-weave model to speed up parallel simulation. I see that timing cache is a "weave-model" structure. So I assume that "Simple" cache (which is default) is not a weave-model structure.

Does this mean that simulation with "Simple" caches is going to be slower because it does not work in accordance with the bound-weave model described in the ZSim ISCA paper? When would I use the bound-weave "Timing" cache over the "Simple" cache?

[gaomy3832]

See #36. My understanding is to use SimpleCache for private caches and TimingCache for shared caches. But normally it seems using SimpleCache for all is good enough. All the test cfg files in this repo use SimpleCache, including pgo.cfg.

[vijay4454]

Ok. Thanks for your response.