medav
commented
4 years ago afaik the prefetcher is intended to live between an L1D and a (private) L2. You can have prefetching on a multi-core/cache system, but essentially you'll need to have 1 prefetcher per core.
I have read all posts about prefetcher, can not found one configuration about the system with multi-core and multi-caches. From the source code of prefetcher.cpp, only one parent and one child is allowed for prefetcher, does that mean the prefetcher can only be enabled for single core system? How to enable prefetcher in multi-core and multi-cache system? Thanks.
My config is as follow:
1 sys = {
2 cores = { 3 c = { 4 › cores = 16; 5 type = "OOO"; 6 dcache = "l1d"; 7 icache = "l1i"; 8 }; 9 }; 10 11 caches = { 12 l1d = { 13 array = { 14 type = "SetAssoc"; 15 ways = 8; 16 }; 17 caches = 16; 18 latency = 1; 19 size = 32768; 20 }; 21 22 l1i = { 23 array = { 24 type = "SetAssoc"; 25 ways = 4; 26 }; 27 caches = 16; 28 latency = 1; 29 size = 32768; 30 }; 31 32 l2 = { 33 array = { 34 type = "SetAssoc"; 35 ways = 8; 36 }; 37 caches = 16; 38 latency = 4; 39 size = 131072; 40 children = "l1i|l1d"; 41 parent = "l3prefetcher"; 42 }; 43 44 l3prefetcher = { 45 isPrefetcher = true; 46 children = "l2"; 47 parent = "l3"; 48 prefetchers = 16; 49 }; 50
51 l3 = { 52 array = { 53 hash = "H3"; 54 type = "SetAssoc"; 55 ways = 16; 56 }; 57 repl = { 58 type = "LRU"; 59 }; 60 type = "Timing"; 61 › banks = 16; 62 caches = 1; 63 latency = 27; 64 #size = 16777216; 65 #size = 4194304; 66 › size = 8388608; 67 children = "l3prefetcher"; 68 }; 69 };
which will complain: [S 0] LOG(LongCache): In func: MemoryController line 33: scheme is:LongCache children = 32, parents=16 children = 16, parents=16 children = 16, parents=1 [S 0] Panic on build/opt/prefetcher.cpp:63: Must have one parent, 16 passed [H] Panic on build/opt/zsim_harness.cpp:119: Child issued a panic, killing simulation