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sabbaghm / c-ll-verilog

An LLVM based mini-C to Verilog High-level Synthesis tool
MIT License
35 stars 9 forks source link

Building c-ll-verilog fails at #include "llvm/Support/CFG.h" #1

Closed SammyTheSnake closed 6 years ago

SammyTheSnake commented 6 years ago

I'm trying to build this project and verilog.cc tries to #include "lvm/Support/CFG.h" which isn't found in any llvm packages in debian, so I'm not sure where it's supposed to come from. Isn't the Control Flow Graph supposed to be defined by your backend? (I'm something of an LLVM n00b, I'm afraid!)

Sam "xanthraxoid" Penny

sabbaghm commented 6 years ago

This project is only evaluated on CentOS (Release: 7.3.1611) with LLVM version 3.4.2. However, you should be able to build it and run it on other distributions as well. Try installing a stable version of LLVM for your distribution (try http://apt.llvm.org) and modify the makefiles inside the parser and codgen folders and the corresponding source files if needed.

For the second part of your question, yes, verilog.cc is part of the code generation phase hence part of the back-end.

SammyTheSnake commented 6 years ago

After hunting around using git, I've found that apparently Support/CFG.h was moved to IR/CFG.h, so I'm trying changing that include path and re-compiling...

That just unveiled a bunch of other errors, unfortunately!

I managed to get it building by downloading the (so out of date no even debian still makes it available without going to the "snapshot" archive) llvm 3.4 and it builds now!

I'm afraid I don't know anywhere near enough C++ to upgrade it to recent versions of llvm, but perhaps doing it a minor release at a time will allow me to pick off errors one at a time and eventually get there :-P

The answer to my second question, by the way, turned out to be "No, CFG.h is part of llvm and doesn't need to come from the backend code" :-)

sabbaghm commented 6 years ago

It is good to hear that you were able to build the project successfully. Upgrading the project to support newer versions of LLVM may be planned soon.

Note that here the Verilog code generation is implemented as an LLVM optimization pass. However, even the intermediate code (IR - which here is LLVM) generation is part of the back-end.

Good luck with your project.