Memory components cannot have virtual bus subcomponents

saeaadl / aadlv2.2

SAE AADL core language, version 2.2

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Memory components cannot have virtual bus subcomponents #46

Open lwrage opened 4 years ago

lwrage commented 4 years ago

Memory components can have both bus and virtual bus access features, but then can only have bus subcomponents. It seems virtual bus subcomponents should be allowed, too.

yoogx commented 4 years ago

As discussed in Toulouse, that seems editorial

jjhugues commented 4 years ago

Proposed resolution

[x] Add virtual bus and bus as subcomponents of memory components