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sahandKashani / SoC-FPGA-Design-Guide

Tutorial for using the DE1-SoC/DE0-Nano-SoC boards for bare-metal and linux programming
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Impossible to generate a preloader with the DE0_Nano_Soc evaluation kit. #13

Open JeromeBeauvais opened 5 years ago

JeromeBeauvais commented 5 years ago

Hello, I have a problem to generate the preloader with the DE0_Nano_Soc. The configuration is the following: Quartus Lite 18.01 and DS5 standard edition V18.01 on Windows 10, I followed the procedure: SoC-FPGA Design Guide DE0-Nano-SoC Edition / LAP – IC – EPFL / Version 1.32 of Sahand Kashani-Akhavan & René Beuchat. I can compile the quartus project without error but with a lot of warning: (826). The list.txt file gives the list of these warning. Where can I find documentation to help me to clear these warning? Then I ran BSP-Editor without problem. Then I change the directory and launch the command “make”: cd C:\intelFPGA\18.1\DE0_Nano_Soc_demo\hw\quartus\software\spl_bsp make I had to modify the path environment variable as follow: QUARTUS_ROOTDIR C:\intelFPGA\18.1\quartus SOPC_KIT_NIOS2 C:\intelFPGA\18.1\nios2eds QSYS_ROOTDIR C:\intelFPGA\18.1\quartus\sopc_builder\bin

But I got this error: Error No rule to make target DS5 uboot-socfpga.tar.gz needed by uboot-socfpga/.untar What can I do ? Thanks for your help Jerome Warning list.txt

sahandKashani commented 5 years ago

Hi Jerome,

Where can I find documentation to help me to clear these warning?

It is normal to have a ton of warnings when compiling in Quartus. Most of those are out of your control and are just byproducts of the way the verilog file for the DDR3 controller is implemented. I never found a way to eliminate them even on my own builds.

It seems you are building the project under Windows. I have never tried that personally so I don't really know if it is any windows-specific issue. Did you use an Embedded Command Shell to launch the commands (and not a Nios II Command Shell)?

JeromeBeauvais commented 5 years ago

Hi SahandKashani Thanks for your fast reply. I used the command shell which is installed with the SocEds Quartus DS5. You can see the image attached. Where can I find a support in this case ? Thanks for your help command prompt

JeromeBeauvais commented 5 years ago

Hi SahandKashani Thanks for your fast reply. I used the command shell which is installed with the SocEds Quartus DS5. You can see the image attached. Where can I find a support in this case ? Thanks for your help command prompt

sahandKashani commented 5 years ago

Based on the image you posted, I think there may be some environment variable missing or something. The path /host_tools/altera/... seems wrong. There must be something before the host_tools part. On my linux machine I have the following: <altera_install_directory>/<version>/embedded/host_tools/ at the beginning of that path.

I would open up that makefile and see what line is generating that error to see what is missing.

JeromeBeauvais commented 5 years ago

Hi SahandKashani Thanks for your fast reply. I added the environment variable C:\intelFPGA\18.1\host_tools\altera\preloader with the full path but the issue is still there. You can see the image attached kind regards path preloader

sahandKashani commented 5 years ago

Sorry, maybe I explained it incorrectly.

It doesn't seem like you need to add anything to your ${PATH}. It looks like a variable inside the makefile you are executing doesn't exist. You should look in the makefile and find the rule that is being executed, and see what variable comes before the /host_tools/altera/... part.

JeromeBeauvais commented 5 years ago

Hi SahandKashani Your explanation is certainly correct but I’m a beginner with Quartus, DS5, Cyclone V and DE0_Nano_Soc. I edited the makefile file to change the path of the variable and the error has changed. We have moved forward one step. I tried to understand the new one and I modified the makefile but I could not fix this the new error. I attached the new error and the makefile. Thanks you very much for your help. error 2 Makefile.txt Jerome

sahandKashani commented 5 years ago

Sorry for my delayed response. These are auto-generated makefiles, so it's hard to tell what's going on...

I've always done all my SoC-FPGA development on linux though, and things work smoothly there. If you want, I can send you a link to a virtual machine which I give students so they can do all these manipulations. It has all tools installed already (Altera 18.0).

JeromeBeauvais commented 5 years ago

Hi SahandKashani Yes it’s a good Idea to try with Linux. I have not a great experience under Linux but the operation is very well documented. Thanks you very much for your help. Jerome

sahandKashani commented 5 years ago

Ok, you can try with the virtual machine available here and see how it goes. The root password is 1234. https://drive.switch.ch/index.php/s/H7qFG1MGxpOVtjl

JeromeBeauvais commented 5 years ago

Hi SahandKashani, I ran the virtual machine with the VM VirtualBox version 5.2.22 of Oracle. I began to execute the first part: 9.1 GENERAL QUARTUS PRIME SETUP. When I want to open the DE0_Nano_SoC_top_level I got a crash screen errors:

top level error opening top level

When I ran the script I got the following errors: error script assignment

Thanks for your help

sahandKashani commented 5 years ago

Hi Jerome,

I checked it out, and I don't understand where that error is coming from... But I realized that if you launch vscode, then double click on a file in quartus, then it opens the file correctly.

Alternatively, you can reset the default text editor to the standard Quartus editor by going to Tools > Options > General > Preferred Text Editor