Opened as a draft to see if you'd want to integrate this functionality into the shipped version. We'd need to do a couple things before it is backwards compatible:
[ ] Make CS optional.
[ ] Add dual edge support back.
Clocks outside chip select low will be ignored. Data captured will include an "index" key with the clock count from the assertion of chip select.
Data frames now span between inactive edges. (Saleae's start on the active edge.) This better mirrors diagrams where data changes around inactive edges. Polarity is also detected at CS assertion and a rising CS edge can be the final inactive edge.
Opened as a draft to see if you'd want to integrate this functionality into the shipped version. We'd need to do a couple things before it is backwards compatible:
Clocks outside chip select low will be ignored. Data captured will include an "index" key with the clock count from the assertion of chip select.
Data frames now span between inactive edges. (Saleae's start on the active edge.) This better mirrors diagrams where data changes around inactive edges. Polarity is also detected at CS assertion and a rising CS edge can be the final inactive edge.