make compile_swemu failure

[zyt1024]

Hello, when I execute make compile_swemu，the following error occurs：

===>The following messages were generated while  performing high-level synthesis for kernel: task_topk Log file: /home/zyt/Project/DeepPoint-V2-FPGA/bui                      ld/_x/task_topk_solution/task_topk/vitis_hls.log :
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:551:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:555:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:559:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:563:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:567:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:571:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:575:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:579:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:583:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/                      kernels/topk_mergesortdf_pe.cpp:587:29

The code specified in the error log that I checked is as follows: code

    #pragma HLS DATAFLOW

    Stream<PairDataIndex_t, 8> streamRead_W1[UnitCount][2];
//#pragma HLS RESOURCE variable=streamRead_W1 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamRead_W1 depth=8

    Stream<PairDataIndex_t, 2> streamW1_W2[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW1_W2 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=2

    Stream<PairDataIndex_t, 4> streamW2_W4[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW2_W4 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=4

    Stream<PairDataIndex_t, 8> streamW4_W8[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW4_W8 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=8

    Stream<PairDataIndex_t, 16> streamW8_W16[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW8_W16 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=16

    Stream<PairDataIndex_t, 32> streamW16_W32[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW16_W32 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=32

    Stream<PairDataIndex_t, 64> streamW32_W64[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW32_W64 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=64

    Stream<PairDataIndex_t, 128> streamW64_W128[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW64_W128 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=128

    Stream<PairDataIndex_t, 256> streamW128_W256[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW128_W256 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=256

    Stream<PairDataIndex_t, 512> streamW256_W512[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW256_W512 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=512

    Stream<PairDataIndex_t, 20> streamW512_Write[UnitCount];
//#pragma HLS RESOURCE variable=streamW512_Write core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=20

[salehjg]

Hi @zyt1024, I hope you are having a wonderful day.

Are you using Vitis?

Unfortunately, the project is not compatible with Vitis and it needs quite a lot of refactoring for that to work since most of the compiler options and directive formats for Vitis have been changed compared to SDx, without backward compatibility.

The project is developed and tested on CentOS 7.6 and Xilinx SDAccel 2019.1.

Also, you can use test/kerneltests to validate the kernels and their results.

[zyt1024]

Hi @zyt1024, I hope you are having a wonderful day.

Are you using Vitis?

Unfortunately, the project is not compatible with Vitis and it needs quite a lot of refactoring for that to work since most of the compiler options and directive formats for Vitis have been changed compared to SDx, without backward compatibility.

The project is developed and tested on CentOS 7.6 and Xilinx SDAccel 2019.1.

Also, you can use test/kerneltests to validate the kernels and their results.

Hi, Thanks, I am using Vitis2021.1, and next I will try to see if Vitis2019.2 is feasible,

[salehjg]

Any update @zyt1024 ? I still suggest using SDAccel 2019.1 to build and run the project out of the box without any refactoring.

[salehjg]

Dear @zyt1024,

I am closing this issue for now, please feel free to re-open it if I could be of any assistance.