search

salessa / likwid

Automatically exported from code.google.com/p/likwid
GNU General Public License v3.0
0 stars 0 forks source link

Add OFFCORE_RESPONSE events to all capable architectures #172

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
Available since Intel Nehalem. They enable monitoring of events that come from 
outside of the core package, like fetching data from memory. Currently only 
implemented for the Intel Silvermont architecture

Original issue reported on code.google.com by Thomas.R...@googlemail.com on 2 Dec 2014 at 2:30

GoogleCodeExporter commented 9 years ago 
My Intel Westmere test machine should have OFFCORE_RESPONSE_0 and 1 but both 
registers are not writable.

Original comment by Thomas.R...@googlemail.com on 4 Dec 2014 at 5:38

GoogleCodeExporter commented 9 years ago 
This issue was closed by revision r481.

Original comment by Thomas.R...@googlemail.com on 12 Feb 2015 at 3:43