Open ThePerfectComputer opened 12 months ago
I can think of two ways to do this.
.vcd
file will include the BRAM contents, which means you can see it in something like gtkwave
.LMK if that helps. Samit
Sounds useful. I guess I'm also wondering how to instantiate a BRAM - couldn't find any example for this.
Also - before switching to RustHDL, I'm wondering if I can probe signals nested in a module hierarchy. VHDL and Verilog support for this is pretty cumbersome requiring "bubbling up" of probes.
For the first one, I would suggest using the BRAM widget, as defined here. An example of logic using the BRAM is here.
For the second - yes! RustHDL simulations are hierarchical, and support automatic inclusion of the entire hierarchy with no additional work on your part. I think if you run the integration tests, you get several examples of deeply nested VCDs you can examine.
Note that this is slightly less true in rhdl
. There, you need to at least flag values that you want to include in the traces. But once flagged, they are composed into hierarchical logs as you would expect. I chose this path since in many cases, a lot of the logging is not only superfluous, but can be so overwhelming that it's hard to find the signals that you actually want. And a multi-GB vcd file can be a pain.
Is there a way to dump BRAM contents during simulation? For example, I may want to step simulation one cycle, and then print BRAM contents - and repeat this process.
If this is possible, how might I go about it?