samprager / fpga

The USRP™ Hardware Driver FPGA Repository
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Vivado cannot find/locate variables from noc_block_pulse_cir_avg.v file. Thus, the simulation window shows all signals as invalid or empty -- no waveform is generated. #2

Open samprager opened 6 years ago

samprager commented 6 years ago

Vivado cannot find/locate variables from noc_block_pulse_cir_avg.v file. Thus, the simulation window shows all signals as invalid or empty -- no waveform is generated.

open_project project_3.xpr open_project project_3.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'. WARNING: [IP_Flow 19-2162] IP 'streaming_fft' is locked:

samprager commented 6 years ago

There's a few things going on here. I have added some changes/comments to the first few lines of noc_block_pulse_cir_avg_tb.sv:

`timescale 1ns/1ps
`define SIM_TIMEOUT_US 50000
`define NS_PER_TICK 1
`define NUM_TEST_CASES 7
`include "sim_exec_report.vh"
`include "sim_rfnoc_lib.svh"
// //wrong path! `include "./noc_block_pulse_cir_avg.v"
// the correct path to this would be:
// `include "../noc_block_pulse_cir_avg.v"
// but i'm not sure why it would need to be included. you are also missing:
`include "sim_rfnoc_lib.svh"
samprager commented 6 years ago

The include definitions at the top of the test bench only need to include files that are not used in the actual design -- vivado will create that hierarchy automatically. The included files here are test-bench specific macros, functions and global variables (ie register addresses).

I went ahead and fixed this by un-commenting the extra `includes and setting the noc_block_pulse_cir_avg_tb.sv files as the simulation 'top module.' This is done in the GUI sidebar with Settings->Simulation top module name