This is the Sancus core supporting DMA controller.; amongst all the changes the most important to be underlined are:
1) the ones in the memory backbone, true arbiter of the DMA interface; it was necessary to implement some control logic for correctly handling the external memory requests with the right hierarchy ( EXT_MEM > EU > FE); a modification of the upstream openMSP430 memory backbone was needed to allow the execution unit to write the PMEM (line 276 of omsp_mem_backbone.v).
2) A change in the omsp_synch_reset module, at the end of the file, where I commented a `ifdef directive on "__SANCUS_SIM" since it was the cause of simulation glitches for the reset signal.
3) Finally, the folder "core/rtl/dma_controller/rtl" is devoted for the verilog code of the controller and its constituent modules.
4) A simple MMIO device is skecthed and programmed to perform both read and write access through DMA interface. Results are shown in the main page (README.md file has been conveniently modified to show simulations results). Simulation program can be found at "core/sim/rtl_sim/src/dma_dev_rd_wr.s43"
This is the Sancus core supporting DMA controller.; amongst all the changes the most important to be underlined are: 1) the ones in the memory backbone, true arbiter of the DMA interface; it was necessary to implement some control logic for correctly handling the external memory requests with the right hierarchy ( EXT_MEM > EU > FE); a modification of the upstream openMSP430 memory backbone was needed to allow the execution unit to write the PMEM (line 276 of omsp_mem_backbone.v).
2) A change in the omsp_synch_reset module, at the end of the file, where I commented a `ifdef directive on "__SANCUS_SIM" since it was the cause of simulation glitches for the reset signal.
3) Finally, the folder "core/rtl/dma_controller/rtl" is devoted for the verilog code of the controller and its constituent modules.
4) A simple MMIO device is skecthed and programmed to perform both read and write access through DMA interface. Results are shown in the main page (README.md file has been conveniently modified to show simulations results). Simulation program can be found at "core/sim/rtl_sim/src/dma_dev_rd_wr.s43"