Closed fritzalder closed 2 years ago
I reverted the extra cycle that broke these tests.
The root cause for the extra cycle for memory glitches in verilator has normally been fixed as per cd88c513e6a079cab951fe3416b034b74ec4c7ae
I tested this locally with sancus-examples and will trigger a CI rebuild as well.
reopening, I was too quick here, we do need the extra cycle indeed, good we have CI :sweat_smile:
hm pinpointed the issue, it seems like DMA accesses can intervene and overwrite the value on the memory bus during the wait cycle :exploding_head:
ext_dmem_en
in the backbone, the exec unit should keep the bus busy during the extra wait cycle I think
normally fixed now, this was a very tricky issue that we would have never found without the (randomized) DMA accesses in the CI tests! ^^
Really nice catch!
In the last PR changes, we broke two of the CI tests: