Closed jdliue closed 3 years ago
How so @jdliue? The SX1278 datasheet, shows bit 0 as controlling the header mode:
@matburnham I think the current source code is correct? 0xfe is 1111 1110. the last bit of the "and" is 0 => explicit mode. 0x01 is 000 0001. The last bit of the "OR" is 1 => implicit mode.
It certainly appears to be. I was having trouble getting implicit mode to work, but the fault was elsewhere. This was one of a number of red herrings.
Likely somewhere else.
How so @jdliue? The SX1278 datasheet, shows bit 0 as controlling the header mode:
Hi, What I saw was as follow After I checked the documentation and found that it was incorrectly quoted from SX1272's datasheet. Thank you for all your replies.
From the register description of data sheet, it seems the code should be changed to void LoRaClass::explicitHeaderMode() { _implicitHeaderMode = 0; writeRegister(REG_MODEM_CONFIG_1, readRegister(REG_MODEM_CONFIG_1) & 0x
fefb); } void LoRaClass::implicitHeaderMode() { _implicitHeaderMode = 1; writeRegister(REG_MODEM_CONFIG_1, readRegister(REG_MODEM_CONFIG_1) | 0x0104); }