Closed GoogleCodeExporter closed 9 years ago
This may be a solution (copy from issue 79 in the er9x thread)
ISR(ADC_vect, ISR_NOBLOCK)
{
static uint8_t chan;
static uint16_t s_ana[8];
static uint16_t ss_ana[8];
static uint16_t sss_ana[8];
ADCSRA = 0; //reset adconv, 13>25 cycles
//if(! keyState(SW_ThrCt)){
s_anaFilt[chan] = (s_anaFilt[chan] + sss_ana[chan]) >> 1;
sss_ana[chan] = (sss_anaFilt[chan] + ss_ana[chan]) >> 1;
ss_ana[chan] = (ss_anaFilt[chan] + s_ana[chan]) >> 1;
s_ana[chan] = (ADC + s_ana[chan]) >> 1;
//}
chan = (chan + 1) & 0x7;
ADMUX = chan | (1<<REFS0); // Multiplexer stellen
STARTADCONV; //16MHz/128/25 = 5000 Conv/sec
}
This would be 4.3 x faster, and give the same rejection.
Original comment by harm.del...@echostar.com
on 2 Sep 2010 at 8:55
use similar algorithm, with adjustable filter depth: 0,1,2,3
uint16_t v=ADC;
uint16_t *filt = (uint16_t*)(s_filtBuf + (uint8_t)(chan*4*2));
for(uint8_t i=g_eeGeneral.adcFilt; i>0; i--,filt++){
uint16_t vn = *filt / 4; //0,16,23,28 vals to 99%
*filt += v - vn; // *3/4
v=vn;
}
asm("":::"memory"); //barrier saves 6 asm-instructions
s_anaFilt[chan] = v;
Original comment by th...@t-online.de
on 8 Sep 2010 at 10:56
See this comment pure as a comment, and not as criticism.
The above algorythm is faster, but does not have equal rejection. Above filter
has 75% glitch rejection (the /4), where the origional in R141 (has /16) and
alternate given by me ( /(2^4) )give 94% rejection.
However, I haven't seen any specification that the filter needs to reject
glitches by 94%, so above algorythm may be fully adequate for the task. We will
see in testing once we have a released label again.
Original comment by harm.del...@echostar.com
on 9 Sep 2010 at 7:53
Original issue reported on code.google.com by
harm.del...@echostar.com
on 2 Sep 2010 at 7:41