SaverECS : A safety verification tool for verification of embedded control software running in closed-loop with plants, under perturbations and different scheduling scenarios.
Adds an automatic compile process with a Makefile.
Removes numerous artifact files that should never have been committed.
Adds a .gitignore so such files are not committed on accident in the future.
Breaks the documentation up into multiple smaller Markdown files, so it's a bit easier to navigate.
A couple of things to note.
If you are going to accept this PR, please also accept my corresponding PR to CProgramToSMT, HERE.
If you do not want to accept these PRs, another good alternative would be to just update the README file on each of the two projects to have a link to my versions of the code, as a useful alternative.
Thank you for developing this interesting tool, and for sharing your code with the open-source community!
This pull request:
Makefile
..gitignore
so such files are not committed on accident in the future.A couple of things to note.
CProgramToSMT
, HERE.Thank you for developing this interesting tool, and for sharing your code with the open-source community!