Closed 0BananaBig0 closed 1 year ago
verible-verilog-format is a tool for formatting Verilog and SystemVerilog code. Part of the Verible tool suite. The more detailed information, you can refer to https://chipsalliance.github.io/verible/ . Thanks.
verible-verilog-format is a tool for formatting Verilog and SystemVerilog code. Part of the Verible tool suite. The more detailed information, you can refer to https://chipsalliance.github.io/verible/ . Thanks.