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scalesim-project / scale-sim-v2

Repository to host and maintain scale-sim-v2 code
MIT License
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Where is the MMIO and interrupt simulation? #72

Closed Z-KN closed 11 months ago

Z-KN commented 1 year ago

In the paper, the authors claim that "The CPU is the bus master which interacts with the accelerator by writing task descriptors to memory-mapped registers inside the accelerator." And in Figure 1 there is an interrupt interface. However I cannot find corresponding code in this codebase. Could you care to point it out for me?

ritikraj7 commented 11 months ago

Hi @Z-KN, the paper describes a model to integrate the accelerator in a system context. However, the interrupt interface is out of scope of this tool.