CSR illegal instruction traps. - Githubissues

scarv / scarv-cpu

SCARV: a side-channel hardened RISC-V platform

MIT License

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CSR illegal instruction traps. #16

Closed ben-marshall closed 4 years ago

ben-marshall commented 4 years ago

Currently, the CPU has no way for the frv_csrs module to indicate a bad write to a CSR field, or non-existent CSR.

[x] Add output wire from frv_csrs to indicate a bad write to a field or a non-existant CSR.
[x] Add illegal opcode trap in writeback stage when this happen.
[x] Test for bad field write
[x] Test for non-existant CSR write.