Spec: multi-precision comparisons

[danpage]

As written, there's a bug with the multi-precision comparisons. These are meant to capture "chained" or digit-wise comparison steps, so accept and produce a flag; at the moment the flag is produced in GPR[rd], but it should also be accepted from say GPR[rs] (or even GPR[rd]) vs. XCR[crs3].

[ben-marshall]

Fixing this requires encoding changes for all three MP comparison instructions. See spec figure 4 for context.

• Bits 14:13 = 3'b111 identify all MP instructions from other ISE instructions.
• Bit 19 currently distinguishes all MP compare instructions from the other "compute" instructions.
• In order to make the flag bit sourcable from the GPRs, the 4 bit crs1 field needs to be made into a 5 bit rs1 field.
• Accomodating this should be as simple as merging bit 19 into the new rs1 field, and using (most likely) bit 31 to distingush between compare v.s compute MP instructions.

I'm about to implement the MP compare instructions now, so I will put all of these changes together into a single commit.

• [x] Specification update (ISE)
• [x] Implementation document
• [x] Binutils changes
• [x] ISE model (verification)
• [x] RTL implementation changes.
• [x] Unit Tests.

[ben-marshall]

Re-open so Dan can sign off on the specification document changes.

[ben-marshall]

@danpage - Do you want to just look over the spec document changes and close this issue if you are satisfied they match what you intended? This is something of a mega-change, so it might be better to sit and go through it together anyway.

[danpage]

I just looked over the spec. document, and it looks fine to me; I'll close the issue.