Performance: Re-write top level instruction accept/execute/retire FSM

[ben-marshall]

• There are some opportunities to drastically increase instruction throughput in the reference implementation.
• There are several edges in the FSM graph where we can retire and accept a new instruction in the same cycle.
• Currently new instructions are accepted only once an old one is retired.

[ben-marshall]

This doesn't need changing for our current implementation.

• Leaving as is makes fewer assumptions about the host CPU and actually makes the design more flexible and easier to use.
• If people want a faster throughput, don't use a co-processor based design, integrated it into your pipeline.