Fix signal used before declaration in multiple Verilog files

scarv / xcrypto

XCrypto: a cryptographic ISE for RISC-V

MIT License

90 stars 10 forks source link

Fix signal used before declaration in multiple Verilog files #85

Closed flaviens closed 1 year ago

flaviens commented 1 year ago

Hi there!

Some tools (e.g., Modelsim) require signals to be declared before being used. There were some violations of this policy in this repository. This PR fixes this problem, without introducing any change to the resulting design.

Thanks! Flavien

danpage commented 1 year ago

Great: thanks a lot!