QEMU RISC-V Logging "Invalid register read" and "Invalid enable write" for the Sifive PLIC

midnightveil commented 6 days ago

I've been experiencing some strange behaviour in QEMU and on real hardware (Star64) with PCIe level-triggered interrupts that I don't see on AArch64 (QEMU or iMX8). I'm not entirely sure whether these are related to this issue, or if this is completely benign, but there's something funny going on. Specifically, in QEMU RISC-V I see a /single/ PCIe interrupt for a level triggered interrupt even when I don't write to the registers to clear it -- so according to PCIe there is still an asserted interrupt -- but I only ever get one from seL4.

Running the microkit hello example, which just prints hello — the client doesn't matter as these errors are printed before the kernel even starts the root task — in QEMU prints out a long series of on boot. qemu-system-riscv64 -machine virt -serial mon:stdio -kernel build/loader.img -m size=2G -nographic -d guest_errors. Interrupts still /somewhat/ work (the timer interrupts are definitely happening), but I don't know what or why these happen. (Or if it's a QEMU issue).

Init local IRQ
sifive_plic_read: Invalid register read 0x208c
sifive_plic_write: Invalid enable write 0x208c
...
Initializing PLIC...
sifive_plic_read: Invalid register read 0x1010
sifive_plic_write: Invalid register write 0x180
sifive_plic_write: Invalid register write 0x184
...
sifive_plic_read: Invalid register read 0x2090
sifive_plic_write: Invalid enable write 0x2090
Booting all finished, dropped to user space

Full boot logs

``` $ qemu-system-riscv64 -machine virt -serial mon:stdio -kernel build/loader.img -m size=2G -nographic -d guest_errors OpenSBI v1.3.1 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|___/_____| | | |_| Platform Name : riscv-virtio,qemu Platform Features : medeleg Platform HART Count : 1 Platform IPI Device : aclint-mswi Platform Timer Device : aclint-mtimer @ 10000000Hz Platform Console Device : uart8250 Platform HSM Device : --- Platform PMU Device : --- Platform Reboot Device : sifive_test Platform Shutdown Device : sifive_test Platform Suspend Device : --- Platform CPPC Device : --- Firmware Base : 0x80000000 Firmware Size : 194 KB Firmware RW Offset : 0x20000 Firmware RW Size : 66 KB Firmware Heap Offset : 0x28000 Firmware Heap Size : 34 KB (total), 2 KB (reserved), 9 KB (used), 22 KB (free) Firmware Scratch Size : 4096 B (total), 760 B (used), 3336 B (free) Runtime SBI Version : 1.0 Domain0 Name : root Domain0 Boot HART : 0 Domain0 HARTs : 0* Domain0 Region00 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: () Domain0 Region01 : 0x0000000080000000-0x000000008001ffff M: (R,X) S/U: () Domain0 Region02 : 0x0000000080020000-0x000000008003ffff M: (R,W) S/U: () Domain0 Region03 : 0x0000000000000000-0xffffffffffffffff M: (R,W,X) S/U: (R,W,X) Domain0 Next Address : 0x0000000080200000 Domain0 Next Arg1 : 0x00000000bfe00000 Domain0 Next Mode : S-mode Domain0 SysReset : yes Domain0 SysSuspend : yes Boot HART ID : 0 Boot HART Domain : root Boot HART Priv Version : v1.12 Boot HART Base ISA : rv64imafdch Boot HART ISA Extensions : time,sstc Boot HART PMP Count : 16 Boot HART PMP Granularity : 4 Boot HART PMP Address Bits: 54 Boot HART MHPM Count : 16 Boot HART MIDELEG : 0x0000000000001666 Boot HART MEDELEG : 0x0000000000f0b509 LDR|INFO: altloader for seL4 starting LDR|INFO: Flags: 0x0000000000000000 LDR|INFO: Kernel: entry: 0xffffffff84000000 LDR|INFO: Root server: physmem: 0x0000000084030000 -- 0x0000000084036000 LDR|INFO: virtmem: 0x000000008a000000 -- 0x000000008a006000 LDR|INFO: entry : 0x000000008a000000 LDR|INFO: region: 0x00000000 addr: 0x0000000084000000 size: 0x000000000002d000 offset: 0x0000000000000000 type: 0x0000000000000001 LDR|INFO: region: 0x00000001 addr: 0x0000000084030000 size: 0x0000000000005e68 offset: 0x000000000002d000 type: 0x0000000000000001 LDR|INFO: region: 0x00000002 addr: 0x000000008402d000 size: 0x00000000000008e8 offset: 0x0000000000032e68 type: 0x0000000000000001 LDR|INFO: region: 0x00000003 addr: 0x000000008402e000 size: 0x0000000000000290 offset: 0x0000000000033750 type: 0x0000000000000001 LDR|INFO: region: 0x00000004 addr: 0x000000008402f000 size: 0x0000000000000030 offset: 0x00000000000339e0 type: 0x0000000000000001 LDR|INFO: copying region 0x00000000 LDR|INFO: copying region 0x00000001 LDR|INFO: copying region 0x00000002 LDR|INFO: copying region 0x00000003 LDR|INFO: copying region 0x00000004 LDR|INFO: enabling MMU LDR|INFO: jumping to kernel Init local IRQ sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x2090 sifive_plic_write: Invalid enable write 0x2090 Bootstrapping kernel Initializing PLIC... sifive_plic_read: Invalid register read 0x1010 sifive_plic_write: Invalid register write 0x180 sifive_plic_write: Invalid register write 0x184 sifive_plic_write: Invalid register write 0x188 sifive_plic_write: Invalid register write 0x18c sifive_plic_write: Invalid register write 0x190 sifive_plic_write: Invalid register write 0x194 sifive_plic_write: Invalid register write 0x198 sifive_plic_write: Invalid register write 0x19c sifive_plic_write: Invalid register write 0x1a0 sifive_plic_write: Invalid register write 0x1a4 sifive_plic_write: Invalid register write 0x1a8 sifive_plic_write: Invalid register write 0x1ac sifive_plic_write: Invalid register write 0x1b0 sifive_plic_write: Invalid register write 0x1b4 sifive_plic_write: Invalid register write 0x1b8 sifive_plic_write: Invalid register write 0x1bc sifive_plic_write: Invalid register write 0x1c0 sifive_plic_write: Invalid register write 0x1c4 sifive_plic_write: Invalid register write 0x1c8 sifive_plic_write: Invalid register write 0x1cc sifive_plic_write: Invalid register write 0x1d0 sifive_plic_write: Invalid register write 0x1d4 sifive_plic_write: Invalid register write 0x1d8 sifive_plic_write: Invalid register write 0x1dc sifive_plic_write: Invalid register write 0x1e0 sifive_plic_write: Invalid register write 0x1e4 sifive_plic_write: Invalid register write 0x1e8 sifive_plic_write: Invalid register write 0x1ec sifive_plic_write: Invalid register write 0x1f0 sifive_plic_write: Invalid register write 0x1f4 sifive_plic_write: Invalid register write 0x1f8 sifive_plic_write: Invalid register write 0x1fc sifive_plic_write: Invalid register write 0x200 sifive_plic_write: Invalid register write 0x204 available phys memory regions: 1 [80200000..100000000] reserved virt address space regions: 3 [ffffffc084000000..ffffffc08402d000] [ffffffc08402d000..ffffffc084030000] [ffffffc084030000..ffffffc084036000] sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x208c sifive_plic_write: Invalid enable write 0x208c sifive_plic_read: Invalid register read 0x2090 sifive_plic_write: Invalid enable write 0x2090 Booting all finished, dropped to user space MON|INFO: Microkit Bootstrap MON|INFO: bootinfo untyped list matches expected list MON|INFO: Number of bootstrap invocations: 0x00000009 MON|INFO: Number of system invocations: 0x00000023 MON|INFO: completed bootstrap invocations MON|INFO: completed system invocations hello, world QEMU: Terminated ```

On a (semi)related note, the setTrigger has HAVE_SET_TRIGGER=1 set even though it does nothing. This is odd.

https://github.com/seL4/seL4/blob/65825d4df8924c3dea07941dc3eac63e7fc32618/include/drivers/irq/riscv_plic0.h#L193-L199

Indanz commented 5 days ago

There may also be a mismatch between the Microkit SDK's/seL4's DTS file and the hardware/QEMU. According to the seL4/tools/dts/star64.dts, PLIC is at 0xc000000.

midnightveil commented 5 days ago

~~This seems to (roughly) match what QEMU was giving me (though a different... size? I can never remember what reg decodes as).~~ Well seL4 derives the DTS for QEMU from the QEMU binary on the host anyway, not from the Star64 one.

And there's an overlay for Star64 in seL4 https://github.com/seL4/seL4/blob/master/src/plat/star64/overlay-star64.dts

Interrupts do (somewhat) work — we have an ethernet and serial driver.

https://github.com/au-ts/sddf/blob/a41d9518e647bc60015b10986a9b0baa2e6dc786/examples/pcie/qemu.dts#L191-L200

https://github.com/seL4/seL4/blob/65825d4df8924c3dea07941dc3eac63e7fc32618/tools/dts/star64.dts#L377-L387

midnightveil commented 5 days ago

Well, looks like it's just something to do with the number of valid IRQs on QEMU - it's 0x5f, so MAX_IRQ should be 95? I guess this changed at some point.

Dunno why I didn't think to just log this before, but feels like this wouldn't be the root cause of either of my issues.

The only one this is not true for is sifive_plic_read: Invalid register read 0x1010.

(Which after changing MAX_IRQ to 95, becomes

Init local IRQ
Bootstrapping kernel
Initializing PLIC...
sifive_plic_write: Invalid register write 0x180

the logs:

Init local IRQ
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 1, hart: 0, bit: 1
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 2, hart: 0, bit: 2
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 3, hart: 0, bit: 3
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 4, hart: 0, bit: 4
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 5, hart: 0, bit: 5
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 6, hart: 0, bit: 6
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 7, hart: 0, bit: 7
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 8, hart: 0, bit: 8
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 9, hart: 0, bit: 9
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 10, hart: 0, bit: 10
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 11, hart: 0, bit: 11
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 12, hart: 0, bit: 12
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 13, hart: 0, bit: 13
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 14, hart: 0, bit: 14
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 15, hart: 0, bit: 15
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 16, hart: 0, bit: 16
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 17, hart: 0, bit: 17
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 18, hart: 0, bit: 18
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 19, hart: 0, bit: 19
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 20, hart: 0, bit: 20
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 21, hart: 0, bit: 21
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 22, hart: 0, bit: 22
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 23, hart: 0, bit: 23
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 24, hart: 0, bit: 24
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 25, hart: 0, bit: 25
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 26, hart: 0, bit: 26
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 27, hart: 0, bit: 27
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 28, hart: 0, bit: 28
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 29, hart: 0, bit: 29
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 30, hart: 0, bit: 30
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 31, hart: 0, bit: 31
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 32, hart: 0, bit: 0
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 33, hart: 0, bit: 1
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 34, hart: 0, bit: 2
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 35, hart: 0, bit: 3
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 36, hart: 0, bit: 4
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 37, hart: 0, bit: 5
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 38, hart: 0, bit: 6
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 39, hart: 0, bit: 7
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 40, hart: 0, bit: 8
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 41, hart: 0, bit: 9
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 42, hart: 0, bit: 10
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 43, hart: 0, bit: 11
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 44, hart: 0, bit: 12
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 45, hart: 0, bit: 13
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 46, hart: 0, bit: 14
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 47, hart: 0, bit: 15
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 48, hart: 0, bit: 16
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 49, hart: 0, bit: 17
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 50, hart: 0, bit: 18
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 51, hart: 0, bit: 19
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 52, hart: 0, bit: 20
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 53, hart: 0, bit: 21
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 54, hart: 0, bit: 22
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 55, hart: 0, bit: 23
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 56, hart: 0, bit: 24
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 57, hart: 0, bit: 25
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 58, hart: 0, bit: 26
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 59, hart: 0, bit: 27
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 60, hart: 0, bit: 28
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 61, hart: 0, bit: 29
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 62, hart: 0, bit: 30
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 63, hart: 0, bit: 31
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 64, hart: 0, bit: 0
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 65, hart: 0, bit: 1
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 66, hart: 0, bit: 2
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 67, hart: 0, bit: 3
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 68, hart: 0, bit: 4
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 69, hart: 0, bit: 5
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 70, hart: 0, bit: 6
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 71, hart: 0, bit: 7
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 72, hart: 0, bit: 8
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 73, hart: 0, bit: 9
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 74, hart: 0, bit: 10
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 75, hart: 0, bit: 11
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 76, hart: 0, bit: 12
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 77, hart: 0, bit: 13
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 78, hart: 0, bit: 14
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 79, hart: 0, bit: 15
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 80, hart: 0, bit: 16
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 81, hart: 0, bit: 17
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 82, hart: 0, bit: 18
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 83, hart: 0, bit: 19
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 84, hart: 0, bit: 20
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 85, hart: 0, bit: 21
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 86, hart: 0, bit: 22
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 87, hart: 0, bit: 23
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 88, hart: 0, bit: 24
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 89, hart: 0, bit: 25
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 90, hart: 0, bit: 26
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 91, hart: 0, bit: 27
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 92, hart: 0, bit: 28
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 93, hart: 0, bit: 29
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 94, hart: 0, bit: 30
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 95, hart: 0, bit: 31
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 96, hart: 0, bit: 0
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 97, hart: 0, bit: 1
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 98, hart: 0, bit: 2
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 99, hart: 0, bit: 3
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 100, hart: 0, bit: 4
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 101, hart: 0, bit: 5
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 102, hart: 0, bit: 6
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 103, hart: 0, bit: 7
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 104, hart: 0, bit: 8
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 105, hart: 0, bit: 9
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 106, hart: 0, bit: 10
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 107, hart: 0, bit: 11
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 108, hart: 0, bit: 12
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 109, hart: 0, bit: 13
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 110, hart: 0, bit: 14
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 111, hart: 0, bit: 15
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 112, hart: 0, bit: 16
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 113, hart: 0, bit: 17
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 114, hart: 0, bit: 18
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 115, hart: 0, bit: 19
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 116, hart: 0, bit: 20
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 117, hart: 0, bit: 21
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 118, hart: 0, bit: 22
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 119, hart: 0, bit: 23
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 120, hart: 0, bit: 24
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 121, hart: 0, bit: 25
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 122, hart: 0, bit: 26
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 123, hart: 0, bit: 27
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 124, hart: 0, bit: 28
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 125, hart: 0, bit: 29
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 126, hart: 0, bit: 30
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 127, hart: 0, bit: 31
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x2090
plic_mask_irq: addr: 0xffffffffc0202090, val: 0x0, irq: 128, hart: 0, bit: 0
sifive_plic_write: Invalid enable write 0x2090
Bootstrapping kernel
Initializing PLIC...
sifive_plic_read: Invalid register read 0x1010
priority, irq: 1
priority, irq: 2
priority, irq: 3
priority, irq: 4
priority, irq: 5
priority, irq: 6
priority, irq: 7
priority, irq: 8
priority, irq: 9
priority, irq: 10
priority, irq: 11
priority, irq: 12
priority, irq: 13
priority, irq: 14
priority, irq: 15
priority, irq: 16
priority, irq: 17
priority, irq: 18
priority, irq: 19
priority, irq: 20
priority, irq: 21
priority, irq: 22
priority, irq: 23
priority, irq: 24
priority, irq: 25
priority, irq: 26
priority, irq: 27
priority, irq: 28
priority, irq: 29
priority, irq: 30
priority, irq: 31
priority, irq: 32
priority, irq: 33
priority, irq: 34
priority, irq: 35
priority, irq: 36
priority, irq: 37
priority, irq: 38
priority, irq: 39
priority, irq: 40
priority, irq: 41
priority, irq: 42
priority, irq: 43
priority, irq: 44
priority, irq: 45
priority, irq: 46
priority, irq: 47
priority, irq: 48
priority, irq: 49
priority, irq: 50
priority, irq: 51
priority, irq: 52
priority, irq: 53
priority, irq: 54
priority, irq: 55
priority, irq: 56
priority, irq: 57
priority, irq: 58
priority, irq: 59
priority, irq: 60
priority, irq: 61
priority, irq: 62
priority, irq: 63
priority, irq: 64
priority, irq: 65
priority, irq: 66
priority, irq: 67
priority, irq: 68
priority, irq: 69
priority, irq: 70
priority, irq: 71
priority, irq: 72
priority, irq: 73
priority, irq: 74
priority, irq: 75
priority, irq: 76
priority, irq: 77
priority, irq: 78
priority, irq: 79
priority, irq: 80
priority, irq: 81
priority, irq: 82
priority, irq: 83
priority, irq: 84
priority, irq: 85
priority, irq: 86
priority, irq: 87
priority, irq: 88
priority, irq: 89
priority, irq: 90
priority, irq: 91
priority, irq: 92
priority, irq: 93
priority, irq: 94
priority, irq: 95
priority, irq: 96
sifive_plic_write: Invalid register write 0x180
priority, irq: 97
sifive_plic_write: Invalid register write 0x184
priority, irq: 98
sifive_plic_write: Invalid register write 0x188
priority, irq: 99
sifive_plic_write: Invalid register write 0x18c
priority, irq: 100
sifive_plic_write: Invalid register write 0x190
priority, irq: 101
sifive_plic_write: Invalid register write 0x194
priority, irq: 102
sifive_plic_write: Invalid register write 0x198
priority, irq: 103
sifive_plic_write: Invalid register write 0x19c
priority, irq: 104
sifive_plic_write: Invalid register write 0x1a0
priority, irq: 105
sifive_plic_write: Invalid register write 0x1a4
priority, irq: 106
sifive_plic_write: Invalid register write 0x1a8
priority, irq: 107
sifive_plic_write: Invalid register write 0x1ac
priority, irq: 108
sifive_plic_write: Invalid register write 0x1b0
priority, irq: 109
sifive_plic_write: Invalid register write 0x1b4
priority, irq: 110
sifive_plic_write: Invalid register write 0x1b8
priority, irq: 111
sifive_plic_write: Invalid register write 0x1bc
priority, irq: 112
sifive_plic_write: Invalid register write 0x1c0
priority, irq: 113
sifive_plic_write: Invalid register write 0x1c4
priority, irq: 114
sifive_plic_write: Invalid register write 0x1c8
priority, irq: 115
sifive_plic_write: Invalid register write 0x1cc
priority, irq: 116
sifive_plic_write: Invalid register write 0x1d0
priority, irq: 117
sifive_plic_write: Invalid register write 0x1d4
priority, irq: 118
sifive_plic_write: Invalid register write 0x1d8
priority, irq: 119
sifive_plic_write: Invalid register write 0x1dc
priority, irq: 120
sifive_plic_write: Invalid register write 0x1e0
priority, irq: 121
sifive_plic_write: Invalid register write 0x1e4
priority, irq: 122
sifive_plic_write: Invalid register write 0x1e8
priority, irq: 123
sifive_plic_write: Invalid register write 0x1ec
priority, irq: 124
sifive_plic_write: Invalid register write 0x1f0
priority, irq: 125
sifive_plic_write: Invalid register write 0x1f4
priority, irq: 126
sifive_plic_write: Invalid register write 0x1f8
priority, irq: 127
sifive_plic_write: Invalid register write 0x1fc
priority, irq: 128
sifive_plic_write: Invalid register write 0x200
priority, irq: 129
sifive_plic_write: Invalid register write 0x204
available phys memory regions: 1
  [80200000..100000000]
reserved virt address space regions: 3
  [ffffffc084000000..ffffffc08402d000]
  [ffffffc08402d000..ffffffc084030000]
  [ffffffc084030000..ffffffc084037000]
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 1, hart: 0, bit: 1
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 2, hart: 0, bit: 2
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 3, hart: 0, bit: 3
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 4, hart: 0, bit: 4
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 5, hart: 0, bit: 5
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 6, hart: 0, bit: 6
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 7, hart: 0, bit: 7
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 8, hart: 0, bit: 8
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 9, hart: 0, bit: 9
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 10, hart: 0, bit: 10
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 11, hart: 0, bit: 11
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 12, hart: 0, bit: 12
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 13, hart: 0, bit: 13
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 14, hart: 0, bit: 14
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 15, hart: 0, bit: 15
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 16, hart: 0, bit: 16
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 17, hart: 0, bit: 17
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 18, hart: 0, bit: 18
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 19, hart: 0, bit: 19
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 20, hart: 0, bit: 20
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 21, hart: 0, bit: 21
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 22, hart: 0, bit: 22
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 23, hart: 0, bit: 23
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 24, hart: 0, bit: 24
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 25, hart: 0, bit: 25
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 26, hart: 0, bit: 26
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 27, hart: 0, bit: 27
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 28, hart: 0, bit: 28
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 29, hart: 0, bit: 29
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 30, hart: 0, bit: 30
plic_mask_irq: addr: 0xffffffffc0202080, val: 0x0, irq: 31, hart: 0, bit: 31
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 32, hart: 0, bit: 0
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 33, hart: 0, bit: 1
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 34, hart: 0, bit: 2
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 35, hart: 0, bit: 3
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 36, hart: 0, bit: 4
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 37, hart: 0, bit: 5
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 38, hart: 0, bit: 6
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 39, hart: 0, bit: 7
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 40, hart: 0, bit: 8
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 41, hart: 0, bit: 9
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 42, hart: 0, bit: 10
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 43, hart: 0, bit: 11
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 44, hart: 0, bit: 12
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 45, hart: 0, bit: 13
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 46, hart: 0, bit: 14
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 47, hart: 0, bit: 15
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 48, hart: 0, bit: 16
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 49, hart: 0, bit: 17
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 50, hart: 0, bit: 18
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 51, hart: 0, bit: 19
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 52, hart: 0, bit: 20
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 53, hart: 0, bit: 21
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 54, hart: 0, bit: 22
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 55, hart: 0, bit: 23
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 56, hart: 0, bit: 24
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 57, hart: 0, bit: 25
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 58, hart: 0, bit: 26
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 59, hart: 0, bit: 27
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 60, hart: 0, bit: 28
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 61, hart: 0, bit: 29
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 62, hart: 0, bit: 30
plic_mask_irq: addr: 0xffffffffc0202084, val: 0x0, irq: 63, hart: 0, bit: 31
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 64, hart: 0, bit: 0
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 65, hart: 0, bit: 1
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 66, hart: 0, bit: 2
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 67, hart: 0, bit: 3
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 68, hart: 0, bit: 4
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 69, hart: 0, bit: 5
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 70, hart: 0, bit: 6
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 71, hart: 0, bit: 7
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 72, hart: 0, bit: 8
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 73, hart: 0, bit: 9
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 74, hart: 0, bit: 10
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 75, hart: 0, bit: 11
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 76, hart: 0, bit: 12
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 77, hart: 0, bit: 13
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 78, hart: 0, bit: 14
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 79, hart: 0, bit: 15
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 80, hart: 0, bit: 16
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 81, hart: 0, bit: 17
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 82, hart: 0, bit: 18
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 83, hart: 0, bit: 19
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 84, hart: 0, bit: 20
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 85, hart: 0, bit: 21
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 86, hart: 0, bit: 22
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 87, hart: 0, bit: 23
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 88, hart: 0, bit: 24
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 89, hart: 0, bit: 25
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 90, hart: 0, bit: 26
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 91, hart: 0, bit: 27
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 92, hart: 0, bit: 28
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 93, hart: 0, bit: 29
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 94, hart: 0, bit: 30
plic_mask_irq: addr: 0xffffffffc0202088, val: 0x0, irq: 95, hart: 0, bit: 31
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 96, hart: 0, bit: 0
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 97, hart: 0, bit: 1
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 98, hart: 0, bit: 2
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 99, hart: 0, bit: 3
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 100, hart: 0, bit: 4
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 101, hart: 0, bit: 5
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 102, hart: 0, bit: 6
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 103, hart: 0, bit: 7
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 104, hart: 0, bit: 8
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 105, hart: 0, bit: 9
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 106, hart: 0, bit: 10
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 107, hart: 0, bit: 11
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 108, hart: 0, bit: 12
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 109, hart: 0, bit: 13
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 110, hart: 0, bit: 14
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 111, hart: 0, bit: 15
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 112, hart: 0, bit: 16
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 113, hart: 0, bit: 17
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 114, hart: 0, bit: 18
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 115, hart: 0, bit: 19
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 116, hart: 0, bit: 20
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 117, hart: 0, bit: 21
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 118, hart: 0, bit: 22
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 119, hart: 0, bit: 23
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 120, hart: 0, bit: 24
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 121, hart: 0, bit: 25
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 122, hart: 0, bit: 26
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 123, hart: 0, bit: 27
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 124, hart: 0, bit: 28
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 125, hart: 0, bit: 29
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 126, hart: 0, bit: 30
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x208c
plic_mask_irq: addr: 0xffffffffc020208c, val: 0x0, irq: 127, hart: 0, bit: 31
sifive_plic_write: Invalid enable write 0x208c
sifive_plic_read: Invalid register read 0x2090
plic_mask_irq: addr: 0xffffffffc0202090, val: 0x0, irq: 128, hart: 0, bit: 0
sifive_plic_write: Invalid enable write 0x2090
Booting all finished, dropped to user space
MON|INFO: Microkit Bootstrap
MON|INFO: bootinfo untyped list matches expected list
MON|INFO: Number of bootstrap invocations: 0x00000009
MON|INFO: Number of system invocations:    0x00000023
MON|INFO: completed bootstrap invocations
MON|INFO: completed system invocations
hello, world
QEMU: Terminated

Indanz commented 5 days ago

src/plat/star64/config.cmake has MAX_IRQ 136, while only 96 seem to work for you.

midnightveil commented 5 days ago

These two changes make this issues disappear.

NB: I'm not quite sure why there's both PLIC_NUM_INTERRUPTS and PLIC_MAX_IRQ.

diff --git a/include/drivers/irq/riscv_plic0.h b/include/drivers/irq/riscv_plic0.h
index 0f5ab066d..bd5fa0b8c 100644
--- a/include/drivers/irq/riscv_plic0.h
+++ b/include/drivers/irq/riscv_plic0.h
@@ -182,7 +182,7 @@ static inline void plic_init_controller(void)
     }

     /* Set the priorities of all interrupts to 1 */
-    for (int i = 1; i <= PLIC_MAX_IRQ + 1; i++) {
+    for (int i = 1; i <= PLIC_MAX_IRQ; i++) {
         writel(2, PLIC_PPTR_BASE + PLIC_PRIO + PLIC_PRIO_PER_ID * i);
     }

diff --git a/src/plat/qemu-riscv-virt/config.cmake b/src/plat/qemu-riscv-virt/config.cmake
index 2bc9cd903..552f12c93 100644
--- a/src/plat/qemu-riscv-virt/config.cmake
+++ b/src/plat/qemu-riscv-virt/config.cmake
@@ -195,7 +195,7 @@ if(KernelPlatformQEMURiscVVirt)
     # practical measurements.
     declare_default_headers(
         TIMER_FREQUENCY 10000000
-        MAX_IRQ 128
+        MAX_IRQ 95
         INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
     )

Indanz commented 5 days ago

NB: I'm not quite sure why there's both PLIC_NUM_INTERRUPTS and PLIC_MAX_IRQ.

Because the first platform IRQ may not start at 1.


diff --git a/include/drivers/irq/riscv_plic0.h b/include/drivers/irq/riscv_plic0.h
index 0f5ab066d..bd5fa0b8c 100644
--- a/include/drivers/irq/riscv_plic0.h
+++ b/include/drivers/irq/riscv_plic0.h
@@ -182,7 +182,7 @@ static inline void plic_init_controller(void)
     }

     /* Set the priorities of all interrupts to 1 */
-    for (int i = 1; i <= PLIC_MAX_IRQ + 1; i++) {
+    for (int i = 1; i <= PLIC_MAX_IRQ; i++) {
         writel(2, PLIC_PPTR_BASE + PLIC_PRIO + PLIC_PRIO_PER_ID * i);
     }

In current code that's already fixed, what seL4 version are you using?

midnightveil commented 5 days ago

https://github.com/seL4/seL4/blob/master/include/drivers/irq/riscv_plic0.h#L185-L188

This does not appear to be fixed? I was looking at the microkit branch.

(... Is this not covered by verification?)

midnightveil commented 5 days ago

Re: number of interrupts, looks like QEMU started with 128 (incl. 0) but then it became 96 at some point?

https://github.com/qemu/qemu/commit/59f74489cf3264035668b4724d4a868ebc6d277c

Here's the current #define: https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h#L102

Indanz commented 5 days ago

This does not appear to be fixed? I was looking at the microkit branch.

Oops, indeed it isn't. I was looking at the loop above that.

(... Is this not covered by verification?)

No, this is hardware specific bootup code, which isn't covered by the proofs.

There doesn't seem to be a way to discover the number of IRQs at runtime, so we can't check it either.

Indanz commented 5 days ago

The ndev property in Microkit's DTS seems to be 0x5f = 95, so maybe we should use that instead of hard-coding MAX_IRQ in the config?

midnightveil commented 5 days ago

Yep, I'd mentioned that earlier. It does at least seem to be hardcoded in QEMU and hasn't changed in several years.

IDK how hard parsing the DTS is in the cmake file. Conceivability that could be done for most platforms as well, but that seems slightly undesirable.

But at the very least could have a script that checks that the MAX_IRQ and DTS file numbers match.

Indanz commented 5 days ago

There is already DTS parsing for some defines, see e.g. tools/hardware/irq.py, but I have no idea how it's used exactly.

Indanz commented 5 days ago

Could you create a pull request with your changes, as well an update for tools/dts/star64.dts to change ndev to 0x5f?

We have a Star64 platform in CI, but it's currently not part of the tested machines.

Indanz commented 5 days ago

Closing this issue as we found the cause and have a solution.

There already is an open issue that says we should use ndev directly instead of the separate define: #1031

seL4 / seL4

QEMU RISC-V Logging "Invalid register read" and "Invalid enable write" for the Sifive PLIC #1350