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seblovett / VLSI

VLSI design project
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Reinvoke ncsim #33

Closed ashleyjr closed 10 years ago

ashleyjr commented 10 years ago

When loading a RAM image reinvoke fucks up on 3rd time

seblovett commented 10 years ago

This has something to do with the reference to the program hex file. If you watch the reinvoke messages, they go: +define+prog_file=\\\"/home/hl13g10/VLSI/Design/Implementation/programs/example270214.hex\\\"

+define+prog_file=\\\\\\\"/home/hl13g10/VLSI/Design/Implementation/programs/example270214.hex\\\\\\\"
ashleyjr commented 10 years ago

Yeh but even when you edit that reference it doesn't resolve itself. Maybe pointing to the hex file by hard coding it in the testbench would fix it but require significantly more coding

seblovett commented 10 years ago

One solution - leave it hard coded to "program.sv". When the sim script runs, it creates a (sym)link from program.sv to the one we want to run?

ashleyjr commented 10 years ago

Cool, I'm going to experiment now, I'll take this bug

ashleyjr commented 10 years ago

http://www.edaboard.co.uk/defining-a-string-macro-from-ncverilog-command-line-t31510.html

Keep this bug alive for a bit, couldn't break it for now

seblovett commented 10 years ago

Still having issues.

ashleyjr commented 10 years ago

Tried using a symlink and just copying the files to the local directory. I think the problem is down to how ncverilog deals with file paths. I know relatives are bad news but this seems odd...

seblovett commented 10 years ago

Are we going to bother to find a solution? I'm happy that we have a work around.

ashleyjr commented 10 years ago

Me too