Closed seblovett closed 10 years ago
OK conventions I propose: All I/Os available at top and bottom of each cell (should be anyway) Stick with above file naming. GPRs (Signals in this order): S1A, S2A, DA, DD, S1D, S2D ALU (signals in this order): A, B, OpCode[4:0], C, V, N, Z, ALUResult, ALUOut From Iain's Lecture, the IR and sign extension are within the same block which ive called IRInterpreter. If I have time I will look into this. Rest of datapath is simple bit-slicing. (Incrementor is just half adder with one input zero, and carry in as 1.
@arr1g13 please try to still with these conventions. If there is a reason for re-ordering signals please post on here any changes. If there is alot to change, please post before making changes.
Also @arr1g13 could you add a copy of your circuit diagram for the GPRs to GIT please? A scan of what you have in your logbook may do
just read ur comments... the copy in my log book is just a rough diagram and i dont think you can understand it???
Ill do a neat diagram and upload it.... ill let you kw if there are any changes in my naming....
@arr1g13 how high is you GPRs cell? My ALU is 1042 per slice, and 1481 for decoder (18153 units overall)
ill just see and let u kw martin because i dint observe the height of the cells.... but i need to get access to the nxclient in order to do tht....
Servers are back up. You can install NX Client on Windows. ( https://www.nomachine.com/download ) I believe you install the full package. If you have trouble, there are some other options (OpenNX is one) that support Windows.
Can you both put up Circuit Diagrams for your slice, and where appropriate, decoder, designs please. They are to be stored in the directory with your magic files. I am happy with scans of logs books, MS Paint or anything. Where your design is more complex (e.g. using different slices), hierarchy will be useful. Thanks.
I have been through the Ir, Pc, regBlock and made them all so that they:
Naming
Just been thinking about all this, and how it fits with the simulation script.
I propose the following hierarchy for the magic files ../c035u/${module}/${module}_slice.mag - individual slice ../c035u/${module}/${module}.mag - full module ../verification/${module}_slice_stim.sv - slice test bench ../verification/${module}_stim.sv - full module test bench (@seblovett to do)
The module names must match those used in the SV behavioural model. Then all the testbenches will run both the behavioural and the magic simulations.
Individual slice tests should be written by the magic designer. By keeping to this, running the sim.py with the module being "${module}_slice" it should work.
@mw92 @arr1g13 can you make your files match these.
Also, can you come up with some magic routing conventions and add them here. To do with inputs and outputs to make the cascading easier.