mw92
commented
10 years ago OK conventions I propose: All I/Os available at top and bottom of each cell (should be anyway) Stick with above file naming. GPRs (Signals in this order): S1A, S2A, DA, DD, S1D, S2D ALU (signals in this order): A, B, OpCode[4:0], C, V, N, Z, ALUResult, ALUOut From Iain's Lecture, the IR and sign extension are within the same block which ive called IRInterpreter. If I have time I will look into this. Rest of datapath is simple bit-slicing. (Incrementor is just half adder with one input zero, and carry in as 1.
@arr1g13 please try to still with these conventions. If there is a reason for re-ordering signals please post on here any changes. If there is alot to change, please post before making changes.
arr1g13
seblovett
Naming
Just been thinking about all this, and how it fits with the simulation script.
I propose the following hierarchy for the magic files ../c035u/${module}/${module}_slice.mag - individual slice ../c035u/${module}/${module}.mag - full module ../verification/${module}_slice_stim.sv - slice test bench ../verification/${module}_stim.sv - full module test bench (@seblovett to do)
The module names must match those used in the SV behavioural model. Then all the testbenches will run both the behavioural and the magic simulations.
Individual slice tests should be written by the magic designer. By keeping to this, running the sim.py with the module being "${module}_slice" it should work.
@mw92 @arr1g13 can you make your files match these.
Also, can you come up with some magic routing conventions and add them here. To do with inputs and outputs to make the cascading easier.