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seblovett / VLSI

VLSI design project
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Cell Lib #66

Closed mw92 closed 10 years ago

mw92 commented 10 years ago

Found an issue with the leftbuf not being half design rule along top edge (I cant route a metal lines over top easily)

seblovett commented 10 years ago

What exactly are you doing? I didn't have any issues during desex 4. Maybe don't put the track so close to the cell?

mw92 commented 10 years ago

Just running metal1 across top, no issues on any other cell. There is a m1-m2 contact which is not 5 units from edge of cell. Im having to add a kink in the wires to resolve.

seblovett commented 10 years ago

Not just push the wire up above all cells by one? Or fix left buf.

mw92 commented 10 years ago

I cba to fix your cell, shifting line up just takes longer and these buf cells are only temporary while testing ALU

seblovett commented 10 years ago

Then it doesn't matter at all surely? If it's just a temporary wrapper, then it's not an issue...

mw92 commented 10 years ago

Just pointing it out as it may cause problems later

seblovett commented 10 years ago

Okay, removing bug label then. Good spot.