contol.sv Optimisation

[ashleyjr]

• [x] Check nWait for all bus access operations
• [x] Take out Decoder functionality which has been replaced by slice17
• [ ] Reduce area once synthesised as much as possible through efficient coding
• [ ] Investigate cracking into two modules to enable 'L' shaped synthesis

[seblovett]

The L shaped synthesis could potentially be done more easily with L-Edit. worth a play around with this week.

[ashleyjr]

Noted, on my todo list for this evening

[seblovett]

Just had a look at the nWait stuff. Fetch cycles have it. Push / Pop does too. Interrupts do not.

For Pop, there is a line (number 687) if(nWait) RegWe = 1; Is this needed? It isn't for any others. All or nothing I say.

[ashleyjr]

I think POP nWait == 1 keeps subState in Cycle3 but if RegWe = 1 it just keep overwritting each time. The solution may be to do the write back in a non-nWait cycle

[seblovett]

But it will write every time, but it will only matter about the last. I guess it means there's never invalid data in there though

[ashleyjr]

There's a complete loop so each clock edge in cycle3 will cause an INC and writeback to the SP, etc

[seblovett]

Ah that makes sense. No worries then.

[seblovett]

There is also something with 0 fanout. Need to remove this possibly.

[seblovett]

Not sure there is much point in doing anything to control. It fits nicely in the pad ring. Can do a bit of postprocessing (moving the I/O to match datapath) but this isn't done in code, and wont really save much space.

[seblovett]

Unless anything drastic can be done, it's not good use of time to do this due to the post-processing efforts involved (a lot of lonely vias occur with the L-Edit layout).