SP setup in Assembler

[ashleyjr]

@mw92 Like the automated setup but just thinking maybe we should have an option for the programmer use R7 as general purpose. Usage...

SP: $python assembler.py foo

NO SP: $python assembler.py -s foobar

[mw92]

surely that would negate the point in having a stack pointer and cause problems when using PUSH, POP, STF, LDF?

[ashleyjr]

Some programs don't require a stack in which case these operations wouldn't be used either, It just gives the programmer slightly more flexibility

[mw92]

Il and it to my list but im not sure if is really useful feature since it means neither stack operations or interrupts can be used

[ashleyjr]

It is simple to do and should be done. In fact we need to explicitly define the initial value of the stack pointer, BIM has asked us to use 0x07D0.

Actually take this out of the functionality out of assembler completely, it should be more of a recommendation in the programmers guide.

[seblovett]

Good point Ashley, I didn't think about the definition not being at top of memory. I think it's best to remove - we don't want to be doing too much as an assembler else programmers may get confused.

[mw92]

ok, but would that not mean the space in memory before the ISR is now completely wasted?

[seblovett]

Program should be split so that the first 14 instructions are done before the ISR, and then a jump occurs to the rest of main. It's a bit of dead space, but should be utilised as much as possible.

[mw92]

would it not be easier having ISR at 2nd location with the first being a jump over it?

[seblovett]

No, jump takes 2 instructions to be able to jump to anywhere in memory. Lowest point ISR could occur is Mem[2]. We chose 16 as an arbitrary location. I'd rather not be changing datapath around at this stage as I'm doing the cadence side of things today. It's half an hours work to on the assembler, that won't affect DRC, or half an hours work on the layout which could affect the DRC.

[mw92]

assembler has now been updated to have no start-up coding, just repositions ISR and adds line in main program to jump over it

[mw92]

Also ISR must be no larger than 126 lines currently

[seblovett]

Can we not utilise the other 14 memory locations? And why is there a restriction on length of ISR?

[mw92]

they are being used as part of amin program is before the ISR. ISR is limited as a branch always instruction has been used which can jump no further than 127 lines. Limit is realistic for this size processor as ISR should never be that long anyway.

[seblovett]

Why not use an absolute JMP? I doubt ISRs will ever be too long, but there is no need of putting a restriction when not necessary - Doesn't sell our CPU! Below should allow a jump to anywhere within a max of 3 instructions. LUI R0 addr[15:7] JMP R0 adddr[4:0] (if addr[7:5] == 0)

Or LUI R0 addr[15:7] LLI R0 addr[7:0] JMP R0 0 (if addr[7:5] != 0)

Plus means you can have main anywhere. Just a bit more flexible.

[mw92]

126 lines is plenty as its only a very basic processor, also a future enhancement I may add is support for out of range jumps, this means it can stay with just the one line.

[seblovett]

I agree, but we can jump to any location easily. There's no point restricting things when there is no need to!