Final Report

[seblovett]

I have added the skeleton outline for the report to the repo. Please have a look through and comment if you have any suggestions.

Work allocations are as below, but programmers guide takes priority. Please check the boxes when you have done / want reviewing.

• [x] Introduction - HSL
• [x] Architecture - HSL
• [x] Instruction Set - MW (this will largely be similar to Programmers Guide. You are allowed to use the same stuff, so don't worry about self plagiarism)

  Design and Implementation:

• [x] Registers - HSL
• [x] ALU - MW
• [x] PC - HSL
• [x] IR - HSL
• [x] Datapath - HSL
• [x] Control - AJR
• [x] CPU - HSL

  Testing

• [x] Registers - HSL
• [x] ALU - MW
• [x] PC - HSL
• [x] IR - HSL
• [x] Datapath - MW
• [x] Control - AJR
• [x] CPU - HSL

  Back Matter

• [x] Conclusion - HSL
• [x] Project Management - HSL
• [x] Division of Labour

Please see the tex files for general outline of what to write about. I will inform when I've edited through.

[arr1g13]

I guess I have to do the introduction too Henry.....

[seblovett]

If you want to do the introduction, you are more than welcome to!

[arr1g13]

ya sure... i will do... Since im at home im not able to work well here but ill complete my part by the next week end by 27th april..... is tht fine??

[seblovett]

Please concentrate on the programmers guide first (#92) before doing this! Programmers guide is due two weeks today, so we need to get on with that!

[seblovett]

Also, earlier would be better. As it's due in later that week, it doesn't give much time for editing. Please can you get something done soon. Even if you're not happy with it, or it's not 100% complete, it gives me something to read and get feedback as to content. @ashleyjr same to you please. Can you crack on with the Programmers Guide.

[arr1g13]

sure.... I will try to do it asp....

[ashleyjr]

@seblovett Will be working on it this week

[mw92]

How are we going about referencing? One references list, or one per chapter that needs it?

[seblovett]

One big one I reckon.

[mw92]

Is there a way of making appendices not start with title in center of page, otherwise the IS Summary will have lots of blank space before starting on next page. Plus appendices arent as important to require a centre page title.

[seblovett]

I'll look into it.

[seblovett]

• [ ] Justify why we don't use sysbus for Lr -> Pc and Alu -> Pc

[seblovett]

I have done the schematic for the regBlock. A few outline standards for the schematics:

• Any tristate bus should use the bus net (I'm aware this is not correct use, but it shows a bus Vs and signal)
• Only use the symbols in the library, exception of hierarchal boxes which should use the symbol layer.
• All I/Os should be named.
• Clock and nReset signals should not be wired

Any more, please add to this list.

[seblovett]

@mw92 - I've had a read through the Instruction Set section and put some green todos for comments. Overall, you seem to have covered it all. However, it's reads more like a story. As we're going to be short on space (max 30 pages for main body), we can't afford this. It should be more documenting what it does and design decisions we made. Other thing is you start saying "in the remaining 10 bits" when there isn't any discussion before this as to format. Should be more of a "A three operand instruction with a total of 8 registers is used because of the space limitiations in a 16bit instruction..."

[seblovett]

@mw92 - more of a coding style suggestion - can you write one sentence per line rather than one paragraph per line. Makes it easier to find a sentence to edit.

[seblovett]

@mw92 - the ALU design section is a bit too long. 8 pages is a significant proportion of our 30, and this is with missing figures, not the full sized ones. I've gone through and made some comments. However, it's difficult to find a lot to crop out as it is well worded and relevant! Have a think, but don't crop anything out until we've got a first draft and we know how much over we are. Overall though, this is good. Couple of dry bits that I've identified. ISA section should be more like this.

[seblovett]

@mw92 - ref your comment about the chapter titles. I have changed these now. However, your table looks unlikely to fit onto the same page. Maybe look into long tables for this? EDIT - in Report.tex, there is a commented line I've added \usepackage{showframe}. If you uncomment this and compile, it will show the text frames and that your table overflows these a lot. It looks unlikely it will fit on the same page as the title.

[mw92]

no offence, but what I have written is not at any standard ready for reviewing, so comments will be ignored until such a time when it is.

[mw92]

@seblovett I dont like your datapath modulear diagram, its confusing, named wrong in places, and I dont think Ir needs to be shown passing around side/top

[mw92]

with div of labour, get rid of the 99-1 split, was a joke there is no need to account for something that was practically nothing

[seblovett]

I have added a macro \review{ Chapter } which will make a yellow to do note. When you have completed a chapter / section / subsection, please use this to indicate to me you want it read. I'll then put any comments in green todos.

[seblovett]

@mw92 - I have removed the figure. I was debating it, but thought it was better to do it then remove it.

[seblovett]

It's looking good! At ~32 pages at the moment - not including @ashleyjr 's code listing. So not much cropping to do. Can everyone have a read through before the meeting today please? Cheers.

[seblovett]

@mw92 - Your Circuit diagrams seem different. Did you use the library I provided? The AND gates look too much like OR gates (and very different from mine) and this confused me when trying to understand one of your circuits.

[mw92]

No, didnt know you had made a library, tried drawing gates myself but I know they are not great

[seblovett]

I mentioned this a few times in meetings. It's located at $HOME/eagle/lbr/c035u.lbr .

[seblovett]

Thinking about it, I'm don't see the advantage of putting the verilog listing in. Anyone got any pressing reasons for keeping it? It's not that spectacular of code.

[seblovett]

Also - thoughts on putting listings of outputs instead of the terminal screen shots?

[seblovett]

I've had a chat to my engineering consultant. He doesn't think that the test results in the back aids to anything, and isn't easy to understand and recommends the removal. Thoughts?

[ashleyjr]

I agree

[seblovett]

@mw92 - Equation~\eqref{eq:DecSUB2} requires 8 gates and is unimplementable. I'm pretty sure it can be implemented. Can there be a reason why you're saying this please.

And I'm pretty sure "unimplementable" is not a work http://dictionary.cambridge.org/spellcheck/british/?q=unimplementable

[mw92]

it cant be implemented using our library as there is no 3 input AND gate

[mw92]

changed word and expanded now

[seblovett]

... but one cascade two AND gates to make a three input AND gate... I'll put "for the same reason" in afterwards then. But surely the reason is the size of the implemented logic, not the lack of being able to.

[mw92]

ok so removing the need for an extra gate to implement it then