r25_7: leftbuf, rightend

seblovett / desex3

Digital IC Design Exercise 3

0 stars 0 forks source link

Closed ashleyjr closed 10 years ago

ashleyjr commented 10 years ago

lonely vias, @seblovett expected because of the inherent spacing in the design

ashleyjr commented 10 years ago

6 total DRC errors but easy to fix

ashleyjr commented 10 years ago

@seblovett For some reason this hasn't fixed the issue. There may need to be some dummy metal1 running vertically nearby. Let's experiment tomorrow.

seblovett commented 10 years ago

Sounds good. I'm going to spend all day in labs to do some GDP testing also.

seblovett commented 10 years ago

This is fixed