cpu16: external reference not synthesizable

[piso77]

While trying to synthesize the cpu16 project, all my toolchains (xilinx ISE and yosys) choke on this:

  assign IP = cpu.regs[7];
  assign zero = cpu.zero;
  assign carry = cpu.carry;
  assign state = cpu.state;

xilinx ise:

Elaborating module <test_CPU16_top>.
Reading initialization file \"home/flag/fpga_stuff/fpga/femto16/fib16.hex\".
ERROR:HDLCompiler:418 - "/home/flag/fpga_stuff/fpga/femto16/cpu16.v" Line 280: External reference <cpu.regs> remains unresolved.
Module test_CPU16_top remains a blackbox, due to errors in its contents
WARNING:HDLCompiler:1499 - "/home/flag/fpga_stuff/fpga/femto16/cpu16.v" Line 263: Empty module <test_CPU16_top> remains a black box.

yosys:

1. Executing Verilog-2005 frontend: cpu16.v
Parsing Verilog input from `cpu16.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\CPU16'.
Generating RTLIL representation for module `\test_CPU16_top'.
cpu16.v:280: Warning: Identifier `\cpu.regs' is implicitly declared.
cpu16.v:280: Warning: Range select out of bounds on signal `\cpu.regs': Setting result bit to undef.
cpu16.v:281: Warning: Identifier `\cpu.zero' is implicitly declared.
cpu16.v:282: Warning: Identifier `\cpu.carry' is implicitly declared.
cpu16.v:283: Warning: Identifier `\cpu.state' is implicitly declared.
Successfully finished Verilog frontend.

Is that a valid Verilog expression at all?

[sehugg]

Hmm, I'm not sure... for me yosys chokes on the "$signed" function but otherwise compiles everything.

Maybe the cpu16.v file has been modified? It seems like it can't find a cpu module declaration in your test file.

[piso77]

I solved the signed extension this way:

https://github.com/piso77/fpga-fun/commit/3c5045fc2560ed227513f547501629fd59ba57e9

and then it'll complain about some signals not being latched:

https://github.com/piso77/fpga-fun/commit/6f9020ac81f08ad99e5f74bdd04932b59ba0a659

After you apply these two, you get the above error.