Custom assembler generates mixed little and big endian numbers

[Beaker73]

I've created a custom assembler json for my verilog project. However when generating 16 bit addresses it uses little endian (what i wanted and expected), but when generating 16 bit constants it uses big endian. The issue can be seen here:

http://8bitworkshop.com/redir.html?platform=verilog&githubURL=https%3A%2F%2Fgithub.com%2FBeaker73%2FVerilog8Bit&file=Rom.v

const.w $2000 generates 0E 20 00 (big endian) instead of the expected 0E 00 20

while call clrVram generates EB 14 00 (little endian) which is expected as the address of clrVram label is at $0014

And while I'm trying to make a little endian CPU, I can image somebody else making a big endian CPU. Maybe it would be handy to add a way to signal the endianess of the numbers in the custom assembler json?

[sehugg]

Hmmm... I'll have to take a look. I'm guessing the label is a fix-up and treated differently than the $2000 constant, but that still shouldn't be. I'll make a test case and figure out why.

If you're building from HEAD, you might want to pull the latest -- there are a couple of new Verilator warnings I had to turn off. And it should show the opcode output of the assembler in the IDE.

btw -- I like what you're doing with your Verilog project so far!

[sehugg]

Now you can define a variable like this: { "bits": 16, "endian": "little" }

Try it on HEAD, or here: https://8bitworkshop.com/dev/

[Beaker73]

Wow, that is fast.

I tried on the dev environment you linked to and the constants now correctly generates little endian values. However adding endianness to the variable now generates 0000 values for addresses. I can work around it for now by defining 2 variables one, with endian config and one without.

I added some variables for automatic, big en little endian and added all combos to the end my 'rom' and pushed the changes.

little label ; generates 0000 WRONG big label ; generates 0400 OK auto label ; generates 0400 OK

little $2000 ; generates 2000 OK big $2000 ; generates 0020 OK auto $2000 ; generates 0020 OK

So issue only seems to be with address label in combination with little endian configuration.

And thanks for you compliment about my Verilog project. It is my first time with Verilog and such a different way of thinking to get used to, compared to normal development. As a kid I started programming on machines like the MSX and the feeling that I might be able to 'build' a machine like that feels nostalgic and empowering at the same time. Bought the Verilog book from amazon to get started.

[sehugg]

Ok, give it a try now. Hope your project goes well.

[sehugg]

Oh, and please let me know if you run into any problems with the dev build! It's a brand-new Verilog engine, and passes more tests than the old engine, but still there might be issues :)

[Beaker73]

It looks perfect now. When marking it with big it generates big endian, when marking it with little it generates little endian. And when not marking it, it is now backwards compatible (the mixed situation) so it won't break existing configurations.

And I'll stay on the dev version and give you my feedback.