In conventional implementations, the clock is synchronized only on the first edge of the data line. This PR implements a mechanism to resynchronize on the rising edge of the data line. This may improve #18
The USB specification allows for some clock errors; in the case of USB LS, even if the RP2040 clock is sufficiently accurate, a 1.5% clock error of device can cause out of sync by around 30 bits (cumulative error exceeds 50%).
This PR implements following features:
Synchronize clock on rise edge by using consecutive jmp instructions
Separate edge detector and NRZI decoder into different state machines
invert both dm/dp pins to merge edge detector and EOP detector
In conventional implementations, the clock is synchronized only on the first edge of the data line. This PR implements a mechanism to resynchronize on the rising edge of the data line. This may improve #18
The USB specification allows for some clock errors; in the case of USB LS, even if the RP2040 clock is sufficiently accurate, a 1.5% clock error of device can cause out of sync by around 30 bits (cumulative error exceeds 50%).
This PR implements following features: