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semidynamics
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OpenVectorInterface
Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
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Questions regarding VL and load / store communications between CPU and VPU
#8
kychentt
closed
1 year ago
4
Questions on UNALIGNED Exception, Retry/Trap Differentiation, Mask_idx Interface, and Dispatch Kill Order
#7
dxie-tt
closed
1 year ago
6
Regarding dispatch.kill signal
#6
ystozlu-tt
closed
1 year ago
1
Clarification on Segment Load/Stores in Version 1.05
#5
dxie-tt
closed
1 year ago
2
About last_idx in MASK_IDX bus
#4
jlong299
closed
2 years ago
2
Maximum number of elements in one unit-load
#3
jlong299
closed
2 years ago
1
How does VPU know which one of the set {1, 2, 4, -1, -2, -4} is the load-stride value?
#2
jlong299
closed
2 years ago
1
Why does vlmul only occupy 2 bits in v_csr?
#1
jlong299
closed
2 years ago
3