RISC-V subsystem - Githubissues

semify-eda / tristan

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RISC-V subsystem #23

Closed adam-hrvth closed 7 months ago

adam-hrvth commented 7 months ago

New modules:

OBI - WB bridge
RAM arbiter
WB RAM interface
Timer

Removed sections for are optimization:

Simple UART
Coprocessor
eXtension Interface
CNTB custom instruction extension