sensille / litehm2

LinuxCNC FPGA board port to LiteX
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Size diff in bit files #5

Closed ozzyrob closed 1 year ago

ozzyrob commented 1 year ago

To begin with, thanks for your work.

Looking forward to getting up and running once I get my hardware, only have a 5a75E V7.1 ATM On Mint 21: riscv64-linux-gnu-gcc (Ubuntu 11.3.0-1ubuntu1~22.04.1) 11.3.0 Release 14.7 - xst P.20131013 (lin64) Installed Litex today July 29 2023 std install nothing fancy

After running make on my machine -rw-rw-r-- 1 fpgadev fpgadev 465580 Jul 29 17:34 rv901t_4out3stepgen_2enc_1pwm.bin -rw-rw-r-- 1 fpgadev fpgadev 465673 Jul 29 17:34 rv901t_4out__3stepgen_2enc_1pwm.bit -rw-rw-r-- 1 fpgadev fpgadev 4194304 Jul 29 17:34 rv901t_4out3stepgen_2enc_1pwm_initial.bin

After extracting from (https://github.com/sensille/litehm2/tree/master/bitstreams) -rw-r--r-- 1 fpgadev fpgadev 465028 Jul 3 03:12 rv901t_4out3stepgen_2enc_1pwm.bin -rw-r--r-- 1 fpgadev fpgadev 465121 Jul 3 03:12 rv901t_4out__3stepgen_2enc_1pwm.bit -rw-r--r-- 1 fpgadev fpgadev 4194304 Jul 3 03:12 rv901t_4out3stepgen_2enc_1pwm_initial.bin

Is the 552 byte difference something to worry about ? Haven't received my RV901t yet so unable to test.

sensille commented 1 year ago

No. The bitstream generation, namely place & route, is a probabilistic process. The results vary slightly from run to run.

ozzyrob commented 1 year ago

Cheers mate. Thanks