How to build River CPU?

sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

http://sergeykhbr.github.io/riscv_vhdl/

Apache License 2.0

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How to build River CPU? #14

Closed mateoconlechuga closed 6 years ago

mateoconlechuga commented 6 years ago

Hello,

I understand that this is a template for instantiating the CPU on an SoC, however I am wondering if it is possible to just instantiate the River CPU as a standalone entity?

I see this issue: https://github.com/sergeykhbr/riscv_vhdl/issues/9

However I am wondering if it is possible to remove any extra components? Thanks for any help!

sergeykhbr commented 6 years ago

Hi, I'm not sure that I correctly understood your question, but:

Yes, you can get River CPU module and connect it to another AXI4 inteconnect. You will also need boot memory, SRAM, interrupt controller, probably Debug Support Unit and other peripheries.
Or you can generate VCD-trace file from SystemC model of River CPU and use it as stimulus for RTL simulation.

mateoconlechuga commented 6 years ago

That makes sense. Do you use any tools to generate the SystemC model from the rtl?

sergeykhbr commented 6 years ago

Thank you for this question.

No, I do not use special tool to generate SystemC I do the following steps in development process:

Functional models of all devices with integration into SoC functional model. Testing.
SystemC model of specific device and automatic comparision of keys parameters relative the functional model.
RTL creation and testing relative SystemC using VCD-stimulus.