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sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
http://sergeykhbr.github.io/riscv_vhdl/
Apache License 2.0
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fix #19 #21

Closed mateoconlechuga closed 6 years ago

mateoconlechuga commented 6 years ago

This fixes the issue of two valid AXI requests when the address ends with "110" instruction wise. Ideally there should only be a loss of a clock or two if a cache miss occurs on an instruction ending with "110", which happens very rarely. I honestly don't see much point of r.double_req, and so it has just been removed entirely.

mateoconlechuga commented 6 years ago

Actually, there appears to be another, more crucial bug. I'll fix that one first and then update this