Closed ashriram closed 2 years ago
Change build.sbt to move to 3.4 Need to redo how verilog and firrtl are printed out in multiple places in test/ e.g., ./src/main/scala/generator/cilk/cilk_for_test06.scala https://github.com/sfu-arch/muir-lib/blob/fea6a314e2ab5d018d7664a2b3ebde6b292675de/src/main/scala/generator/cilk/cilk_for_test06.scala#L360
This has to be replaced by the new Chisel stage https://www.chisel-lang.org/api/latest/chisel3/stage/ChiselStage.html
Easy way is to replicate what's in the bootcamp. Create an object that does it https://github.com/sfu-arch/chisel-template/blob/797b0254f86e7dfa91ba5dfa1603529d66343048/example.sc#L26 Make sure all dependencies are included e.g., breeze, treadle, diagrammer etc for visualization
Make sure all dependencies are included e.g., breeze, treadle, diagrammer etc for visualization
/ This will cause File IO to happen because it's a Stage / (new ChiselStage).emitVerilog(new Foo)
/ This will not cause any File IO, it just returns a string. This just a bag of phases. / that returns a string ChiselStage.emitVerilog(new Foo)
Upgraded to 3.5
ashriram
commented
2 years ago ashriram
commented
2 years ago
Change build.sbt to move to 3.4 Need to redo how verilog and firrtl are printed out in multiple places in test/ e.g., ./src/main/scala/generator/cilk/cilk_for_test06.scala https://github.com/sfu-arch/muir-lib/blob/fea6a314e2ab5d018d7664a2b3ebde6b292675de/src/main/scala/generator/cilk/cilk_for_test06.scala#L360
This has to be replaced by the new Chisel stage https://www.chisel-lang.org/api/latest/chisel3/stage/ChiselStage.html
Easy way is to replicate what's in the bootcamp. Create an object that does it https://github.com/sfu-arch/chisel-template/blob/797b0254f86e7dfa91ba5dfa1603529d66343048/example.sc#L26
Make sure all dependencies are included e.g., breeze, treadle, diagrammer etc for visualization/ This will cause File IO to happen because it's a Stage / (new ChiselStage).emitVerilog(new Foo)
/ This will not cause any File IO, it just returns a string. This just a bag of phases. / that returns a string ChiselStage.emitVerilog(new Foo)