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sgherbst / anasymod

A framework for FPGA emulation of mixed-signal systems
BSD 3-Clause "New" or "Revised" License
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Add support for EDIF files and update Zynq UART support #13

Closed sgherbst closed 4 years ago

sgherbst commented 4 years ago

Summary

This PR adds support for EDIF files (vendor-neutral gate-level netlists), which makes it easier to work with IPs from tools outside of the Xilinx ecosystem. It also updates the existing Zynq UART code and includes testing of the UART capabilities in the regression test.

UART updates

  1. Allowed the user to provide their own firmware files, including main.c (this is useful to fill the performance/flexibility gap between synthesizable test features and Python-driven test features).
  2. Added firmware generator that produces get_ and set_ C functions for signals registered in the sim control YAML file.
  3. Added automation for xsct for building the *.elf file and downloading it to the FPGA.
  4. Added control bit valid to the control interface for Zynq CPU outputs, which allows the user to set up the register address and data without updating the register outputs.
codecov-commenter commented 4 years ago

Codecov Report

Merging #13 into master will increase coverage by 4.19%. The diff coverage is 92.77%.

Impacted file tree graph

@@            Coverage Diff             @@
##           master      #13      +/-   ##
==========================================
+ Coverage   69.27%   73.47%   +4.19%     
==========================================
  Files          59       65       +6     
  Lines        3906     4075     +169     
==========================================
+ Hits         2706     2994     +288     
+ Misses       1200     1081     -119
Impacted Files Coverage Δ
anasymod/analysis.py 61.90% <70.00%> (+0.50%) :arrow_up:
anasymod/filesets.py 64.73% <70.58%> (+0.40%) :arrow_up:
anasymod/generators/vivado.py 80.55% <77.77%> (-0.64%) :arrow_down:
anasymod/emu/vivado_emu.py 92.18% <80.00%> (+0.52%) :arrow_up:
anasymod/sources.py 75.60% <83.33%> (+0.60%) :arrow_up:
anasymod/generators/gen_api.py 81.48% <88.88%> (+0.23%) :arrow_up:
anasymod/emu/xsct_emu.py 100.00% <100.00%> (ø)
anasymod/fpga_boards/boards.py 100.00% <100.00%> (ø)
anasymod/generators/xsct.py 100.00% <100.00%> (ø)
anasymod/sim_ctrl/uart_ctrlapi.py 47.56% <100.00%> (+17.07%) :arrow_up:
... and 22 more

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