This PR adds support for the ZCU106 board. This turned out to be a bit involved, not only because it is the first UltraScale+ board that we have looked at, but also because it has an unusual problem with the DDR4 chips used on the board.
Details
FPGA board definitions now have an optional is_ultrascale property (defaults to False)
The PS block diagram generator is updated to support the UltraScale+ PS, which looks a bit different than the Zynq PS.
When the UltraScale+ PS is used, the external I/Os should not be routed through to the top level RTL, so that detail is taken care of as well.
The XSCT programming template is updated so that it uses the FSBL flow for UltraScale+ boards, and the TCL flow for other boards. This is required for ZCU106, since it only works with the FSBL flow (more information here)
Added an optional vivado_stack setting to the prj.yaml file. For UltraScale+ designs, sometimes it is necessary to set this to 2000 to prevent Vivado from freezing. It might just be an issue on older computers like mine, though.
Summary
This PR adds support for the ZCU106 board. This turned out to be a bit involved, not only because it is the first UltraScale+ board that we have looked at, but also because it has an unusual problem with the DDR4 chips used on the board.
Details
is_ultrascaleproperty (defaults toFalse)vivado_stacksetting to theprj.yamlfile. For UltraScale+ designs, sometimes it is necessary to set this to2000to prevent Vivado from freezing. It might just be an issue on older computers like mine, though.