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sgherbst / anasymod

A framework for FPGA emulation of mixed-signal systems
BSD 3-Clause "New" or "Revised" License
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Small updates to support a non-emulation use case #40

Closed sgherbst closed 3 years ago

sgherbst commented 3 years ago

This small PR includes a few updates to support a non-emulation use case running at a relatively high frequency.

  1. New TCLFile type allowing users to add custom TCL code to the Vivado build process. I'm using this to instantiate new IPs using TCL rather XCI, which can be a bit more portable & flexible.
  2. New option for prj.yaml: no_time_manager. Causes the Verilog generation to not include the time manager and its associated collateral. The main purpose for this is to avoid limiting the maximum operating frequency of the project. As part of this bypass, emu_clk_2x ends up simply being wiring directly to emu_clk, so the user should note that emu_clk will be twice as fast as specified in prj.yaml when this option is used.
  3. wait_on_and_dump_trace has a new argument emu_time_scaled which is passed straight through to the ConvertWaveform object, which already has that argument.
  4. Implemented emu_time_scaled argument for CSV -> VCD conversion in ConvertWaveform. This is useful when no_time_manager is used.
  5. Fixed two small bugs in module_clk_manager.py

UPDATE 12/4/2020: I have also used this as an opportunity to add Windows to the platforms tested with GitHub actions, and to add preliminary support of the ZCU102 board. This addresses issues #10 and #41.

sgherbst commented 3 years ago

Temporarily closing PR to work through a problem with the new Windows regression tests.

sgherbst commented 3 years ago

Reopening after resolving issue in Windows regression tests.