Handling of VIO analog signals + Add test of msdsl functions

[sgherbst]

Summary

This PR mainly has to do with reading / writing analog signals using the VIO and the sim_ctrl module.

Update to analog control signals

1. Default values for VIO analog inputs are now treated as real numbers, and converted to the appropriate fixed-point representation. In other words, the initial value specified for analog control inputs in simctrl.yaml should be a real value.
2. The function set_param now takes a real value and converts it to the appropriate fixed-point representation (for analog control inputs only; the behavior for digital control inputs is unaffected.)
3. Similarly, the value returned by get_param is now a real number (for analog control outputs only)
4. Analog I/O in the sim_ctrl module is now handled using the svreal macros `DECL_REAL, `INPUT_REAL and `OUTPUT_REAL. This works because the generated top-level verilog now uses `PASS_REAL to pass formatting information. One advantage of this approach is that is is possible to switch to a floating-point representation for sim_ctrl by setting the `FLOAT_REAL flag.
5. The rc regression testing example is updated to use these new features.

Other changes

1. Added a new regression test called function that implements a sine function using the new make_function feature from msdsl.
2. Added a GitHub action for releasing to PyPI
3. Refactored the regression script into a file called regress.sh
4. Bumped the anasymod version to 0.2.2

[codecov-io]

Codecov Report

Merging #6 into master will increase coverage by 0.37%. The diff coverage is 100%.

@@            Coverage Diff             @@
##           master       #6      +/-   ##
==========================================
+ Coverage   62.61%   62.98%   +0.37%     
==========================================
  Files          59       59              
  Lines        3472     3472              
==========================================
+ Hits         2174     2187      +13     
+ Misses       1298     1285      -13

Impacted Files	Coverage Δ
anasymod/structures/module_viosimctrl.py	87.5% <ø> (ø)	:arrow_up:
anasymod/templates/vio_wiz.py	83.33% <100%> (+4.54%)	:arrow_up:
anasymod/sim_ctrl/datatypes.py	86% <100%> (+7.73%)	:arrow_up:
anasymod/generators/gen_api.py	80.72% <100%> (+1.83%)	:arrow_up:
anasymod/sim_ctrl/vio_ctrlapi.py	58.75% <100%> (+1.44%)	:arrow_up:
anasymod/structures/module_top.py	88.54% <0%> (-0.77%)	:arrow_down:
anasymod/structures/structure_config.py	79.87% <0%> (+1.88%)	:arrow_up:
anasymod/templates/launch_FPGA_sim.py	90% <0%> (+2.5%)	:arrow_up:

---

Continue to review full report at Codecov.

Legend - Click here to learn more Δ = absolute <relative> (impact), ø = not affected, ? = missing data Powered by Codecov. Last update 6162108...3fe77c0. Read the comment docs.