Updates to emulation control

[sgherbst]

Summary

This PR adds several new features to emulation control, such as being able to run the emulation for a certain amount of time and stall the emulation. It also simplifies the use case in which there is only one emulation clock that uses a fixed timestep.

Emulation time updates

1. Emulation time and timestep requests are now always represented using unsigned integers whose scale factor is given by dt_scale, which has decade units like 1e-15, 1e-12, etc. This makes it easier to interpret raw waveforms with timestep requests, and also removes the ambiguity associated with equality comparisons of real numbers (which were used to determine if timestep requests were granted).
2. When there is no block that requests timestep, anasymod automatically inserts a block at the top level (osc_model_anasymod) that requests a timestep of `EMU_DT. This allows the "no dt req" case to be handled in the same way as the "dt req" case.
3. Anaysmod also instantiates a block at the top level (ctrl_anasymod) that makes a timestep request based on user input, and this is used to implement features like stalling or running for a certain amount of time.

Emulation control updates

1. For emulation, some new control functions are added:
   1. stall_emu: Stop emulation from running (i.e., set timestep request to zero)
   2. sleep_emu: Run emulation for a given amount of time and then stop
   3. get_emu_time: Return the current emulation time
2. For simulation, the same features are available as a tasks and functions from a header called anasymod.sv
3. For now anasymod.sv has to be included in the body of a module definition. We can explore ways to make this more convenient in the future.

Detail on the "no dt req" case

When no blocks request a timestep, a block is instantiated at the top level that requests one timestep every EMU_DT seconds. The output of the block is a clock enable signal, which is routed to blocks usingCKE_MSDSL. MSDSL will be updated soon to make use of this signal, which essentially allows the user to freeze time for all analog blocks.

Other changes

1. Vivado and Icarus verilog simulations now check the output text for error strings, so that we can raise an exception even if the simulator does not return an error code.
2. Regression testing with Icarus verilog is done using GitHub actions.
3. Did some code reformatting to make it easier to read code on a small screen.

[codecov-io]

Codecov Report

Merging #7 into master will increase coverage by 0.42%. The diff coverage is 74.68%.

@@            Coverage Diff             @@
##           master       #7      +/-   ##
==========================================
+ Coverage   62.98%   63.40%   +0.42%     
==========================================
  Files          59       59              
  Lines        3472     3613     +141     
==========================================
+ Hits         2187     2291     +104     
- Misses       1285     1322      +37     

Impacted Files	Coverage Δ
anasymod/generators/gen_api.py	81.25% <ø> (+0.52%)	:arrow_up:
anasymod/probe.py	0.00% <0.00%> (ø)
anasymod/templates/execute_FPGA_sim.py	21.42% <9.09%> (-6.35%)	:arrow_down:
anasymod/wave.py	60.15% <52.38%> (-0.19%)	:arrow_down:
anasymod/structures/structure_config.py	63.73% <55.35%> (-16.15%)	:arrow_down:
anasymod/analysis.py	55.83% <71.42%> (+0.45%)	:arrow_up:
anasymod/emu/vivado_emu.py	88.33% <71.42%> (ø)
anasymod/sim_ctrl/datatypes.py	81.15% <81.39%> (-4.85%)	:arrow_down:
anasymod/structures/module_traceport.py	91.66% <83.33%> (-2.46%)	:arrow_down:
anasymod/util.py	61.72% <83.33%> (+9.09%)	:arrow_up:
... and 23 more

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