sgherbst / pysvinst

Python library for parsing module definitions and instantiations from SystemVerilog files
MIT License
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Instance name defined in a text macro doesn't work #10

Closed sgherbst closed 3 years ago

sgherbst commented 3 years ago

Example:

`define MOD_INST u_mysubmod
module mymod;
mysubmod `MOD_INST (); 
endmodule

Output:

files:
  - file_name: "some_file.sv"
    defs:
      - mod_name: "mymod"
        insts:

Expected:

files:
  - file_name: "some_file.sv"
    defs:
      - mod_name: "mymod"
        insts:
          - mod_name: "mysubmod"
            inst_name: "u_mysubmod"
sgherbst commented 3 years ago

This issue still seems to be present with sv-parser 0.8.2. I filed an issue about it in that project (https://github.com/dalance/sv-parser/issues/20). For what it's worth, you can work around the issue for now by making the macro a function with a dummy argument, like this:

`define MOD_INST(x) u_mysubmod
module mymod;
mysubmod `MOD_INST(x) (); 
endmodule